AD7467 Analog Devices, AD7467 Datasheet - Page 17

• Manufacturer Part Number: AD7467
• Description: 1.6 V Micro-Power 10-Bit ADC
• Manufacturer: Analog Devices

Specifications of AD7467

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7466/AD7467/AD7468 are fast, micropower, 12-bit,
10-bit, and 8-bit ADCs, respectively. The parts can be operated
from a 1.6 V to 3.6 V supply. When operated from any supply
voltage within this range, the AD7466/AD7467/AD7468 are
capable of throughput rates of 200 kSPS when provided with a
3.4 MHz clock.
The AD7466/AD7467/AD7468 provide the user with an on-
chip track-and-hold, an ADC, and a serial interface housed in a
tiny 6-lead SOT-23 or an 8-lead MSOP package, which offer the
user considerable space-saving advantages over alternative
solutions. The serial clock input accesses data from the part, but
also provides the clock source for the successive approximation
ADC. The analog input range is 0 V to V
ence is not required for the ADC, and there is no on-chip
reference. The reference for the AD7466/AD7467/AD7468 is
derived from the power supply, thus giving the widest possible
dynamic input range.
The AD7466/AD7467/AD7468 also feature an automatic
power-down mode to allow power savings between conversions.
The power-down feature is implemented across the standard
serial interface, as described in the Normal Mode section.
CONVERTER OPERATION
The AD7466/AD7467/AD7468 are successive approximation
analog-to-digital converters based around a charge redistribu-
tion DAC. Figure 19 and Figure 20 show simplified schematics
of the ADC. Figure 19 shows the ADCs during the acquisition
phase. SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on V
When the ADC starts a conversion, as shown in Figure 20,
SW2 opens and SW1 moves to Position B, causing the com-
parator to become unbalanced. The control logic and the
charge redistribution DAC are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. When the com-
parator is rebalanced, the conversion is complete. The control
logic generates the ADC output code. Figure 21 shows the ADC
transfer function.
V
IN
A
SW1
AGND
B
CAPACITOR
SAMPLING
ACQUISITION
V
PHASE
Figure 19. ADC Acquisition Phase
DD
/2
IN
.
SW2
COMPARATOR
DD
. An external refer-
REDISTRIBUTION
CHARGE
CONTROL
LOGIC
DAC
Rev. C | Page 17 of 28
ADC TRANSFER FUNCTION
The output coding of the AD7466/AD7467/AD7468 is straight
binary. The designed code transitions occur at successive
integer LSB values; that is, 1 LSB, 2 LSB, and so on. The LSB size
for the devices is as follows:
The ideal transfer characteristics for the devices are shown in
Figure 21.
TYPICAL CONNECTION DIAGRAM
Figure 22 shows a typical connection diagram for the devices.
V
be well decoupled. This provides an analog input range of
0 V to V
680nF
0V TO V
V
IN
REF
INPUT
V
V
V
is taken internally from V
DD
DD
DD
DD
Figure 21. AD7466/AD7467/AD7468 Transfer Characteristics
240μA
A
SW1
DD
/4096 for the AD7466
/1024 for the AD7467
/256 for the AD7468
AGND
B
.
GND
V
V
CAPACITOR
IN
111...111
111...110
111...000
011...111
000...010
000...001
000...000
SAMPLING
DD
Figure 22. REF192 as Power Supply to AD7466
0.1μF
CONVERSION
PHASE
AD7466
V
Figure 20. ADC Conversion Phase
DD
0V 1LSB
/2
TANT
1μF
2.5V
AD7466/AD7467/AD7468
SDATA
SCLK
SW2
CS
REF192
DD
ANALOG INPUT
1LSB = V
1LSB = V
1LSB = V
and, therefore, V
+V
COMPARATOR
DD
10μF
INTERFACE
DD
DD
DD
SERIAL
– 1LSB
/4096 (AD7466)
/1024 (AD7467)
/256 (AD7468)
0.1μF
REDISTRIBUTION
DD
CHARGE
CONTROL
LOGIC
DAC
should
5V
SUPPLY
μC/μP