AD9432 Analog Devices, AD9432 Datasheet - Page 14

• Manufacturer Part Number: AD9432
• Description: 12-Bit, 105 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9432

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 105MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD9432
DIGITAL OUTPUTS
The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL-/CMOS-
compatible for lower power consumption. The output data
format is twos complement (see Table 6).
Table 6. Twos Complement Output Coding (V
Code
+2047
…
0
−1
…
−2048
The out-of-range (OR) output is logic low for normal operation.
During any clock cycle when the ADC output data (Dx) reaches
positive or negative full scale (+2047 or −2048), the OR output
goes high. The OR output is internally generated each clock cycle.
It has the same pipeline latency and propagation delay as the ADC
output data and remains high until the output data reflects an
in-range condition. The ADC output bits (Dx) do not roll over
and, therefore, remain at positive or negative full scale (+2047
or −2048) while the OR output is high.
AIN − AIN (V)
1.000
…
0
−0.00049
…
−1.000
Digital Output
0111 1111 1111
…
0000 0000 0000
1111 1111 1111
…
1000 0000 0000
REF
= 2.5 V)
Rev. F | Page 14 of 16
VOLTAGE REFERENCE
A stable and accurate 2.5 V voltage reference is built into the
AD9432 (VREFOUT). In normal operation, the internal refer-
ence is used by strapping Pin 45 to Pin 46 and placing a 0.1 μF
decoupling capacitor at VREFIN.
The input range can be adjusted by varying the reference voltage
applied to the AD9432. No appreciable degradation in performance
occurs when the reference is adjusted ±5%. The full-scale range
of the ADC tracks reference voltage changes linearly.
TIMING
The AD9432 provides latched data outputs, with 10 pipeline
delays. Data outputs are included or available one propagation
delay (t
Figure 2). The length of the output data lines and the loads
placed on them should be minimized to reduce transients
within the AD9432; these transients can detract from the
dynamic performance of the converter.
The minimum guaranteed conversion rate of the AD9432 is
1 MSPS. At internal clock rates below 1 MSPS, dynamic perfor-
mance may degrade. Therefore, input clock rates below 1 MHz
should be avoided.
During initial power-up, or whenever the clock to the AD9432
is interrupted, the output data will not be accurate for 200 ns or
10 clock cycles, whichever is longer.
PD
) after the rising edge of the encode command (see