AD7859 Analog Devices, AD7859 Datasheet - Page 3

• Manufacturer Part Number: AD7859
• Description: 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit, Parallel Sampling ADCs
• Manufacturer: Analog Devices

Specifications of AD7859

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: LCC,QFP

Parameter
CONVERSION RATE
POWER REQUIREMENTS
SYSTEM CALIBRATION
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
REV. A
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7859/AD7859L can calibrate. Note also that these are voltage spans
Temperature range as follows: A, B Versions, –40 C to +85 C.
Specifications apply after calibration.
SNR calculation includes distortion and noise components.
Not production tested, guaranteed by characterization at initial product release.
All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DV
Analog inputs @ AGND.
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
This is explained in more detail in the calibration section of the data sheet.
Conversion Time
Track/Hold Acquisition Time
AV
I
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
Offset Calibration Span
Gain Calibration Span
DD
Normal Mode
Sleep Mode
With External Clock On
With External Clock Off
DD,
With External Clock On
With External Clock Off
DV
DD
6
5
7
7
A Version
4.5 (10)
0.5 (1)
+3.0/+5.5
5.5 (1.95)
5.5 (1.95)
10
400
5
200
30 (10)
20 (6.5)
55
36
27.5
18
+0.05
+1.025
V
REF
1
V
REF
/–0.05
B Version
4.5
0.5
+3.0/+5.5
5.5
5.5
10
400
5
200
30 (10)
20 (6.5)
55
36
27.5
18
/–0.975
V
REF
V
1
REF
Units
V min/max
mA max
mA max
mW max
mW max
V max/min
V max/min
s max
s min
A typ
A typ
A max
A typ
W typ
W typ
W max
W max
–3–
DD
. No load on the digital outputs. Analog inputs @ AGND.
Test Conditions/Comments
t
(L Versions Only, 0 C to +70 C, 1.8 MHz CLKIN)
(L Versions Only, –40 C to +85 C, 1.8 MHz CLKIN)
AV
AV
Full Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1.
Typically 1 A. Full Power-Down. Power Management
Bits in Control Register Set as PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1.
V
V
V
V
V
V
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibration
CLKIN
DD
DD
DD
DD
DD
DD
DD
DD
= 5.5 V: Typically 25 mW (8); SLEEP = V
= 3.6 V: Typically 15 mW (5.4); SLEEP = V
= 5.5 V; SLEEP = 0 V
= 3.6 V; SLEEP = 0 V
= 5.5 V: Typically 5.5 W; SLEEP = 0 V
= 3.6 V: Typically 3.6 W; SLEEP = 0 V
= DV
= DV
18
DD
DD
= 4.5 V to 5.5 V. Typically 4.5 mA
= 3.0 V to 3.6 V. Typically 4.0 mA
DD
AD7859/AD7859L
. No load on the digital outputs.
DD
REF
DD
0.025
0.05
V
V
REF
REF
).
,