AD7701 Analog Devices, AD7701 Datasheet - Page 6

• Manufacturer Part Number: AD7701
• Description: 16-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7701

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 16kSPS
• Interface: Ser
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 2.5V,Uni 2.5V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC,SOP

AD7701
TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
SSC MODE
t
t
t
t
t
t
t
SEC MODE
f
t
t
t
t
t
t
AC MODE
t
t
t
NOTES
10
11
Specifications subject to change without notice.
1
2
3
4
5
6
7
8
9
CLKIN
r
f
1
2
3
4
5
6
7
8
9
10
SCLK
11
12
13
14
15
16
17
18
19
Sample tested at 25°C to ensure compliance. All input signals are specified with t
See Figures 1 to 6.
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
The AD7701 is production tested with f
Specified using 10% and 90% points on waveform of interest.
In order to synchronize several AD7701s together using the SLEEP pin, this specification must be met.
t
t
If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
5
5
draw higher current than specified and possibly become uncalibrated.
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
SDATA is clocked out on the falling edge of the SCLK input.
6
7
8
4
9
8, 9
7, 10
11
8
8
, t
and t
10
, t
3, 4
13
15
, and t
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
16
Limit at T
(A, B Versions)
200
5
200
5
50
50
0
50
1000
3/f
100
250
300
790
l/f
(4/f
5
35
160
160
150
250
200
40
180
200
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
CLKIN
CLKIN
CLKIN
+200
) +200
MIN
, T
MAX
CLKIN
at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
Limit at T
(S, T Versions)
200
5
200
5
50
50
0
50
1000
3/f
100
250
300
790
l/f
(4/f
5
35
160
160
150
250
200
40
180
200
1, 2
CLKIN
CLKIN
CLKIN
(AV
4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV
+200
) +200
DD
MIN
= DV
, T
DD
MAX
= +5 V
Unit
kHz min
MHz max
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns max
MHz
ns min
ns min
ns max
ns max
ns max
ns max
ns min
ns max
ns max
–6–
r
= t
10%; AV
f
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Conditions/Comments
Master Clock Frequency: Internal Gate Oscillator.
Typically 4.096 MHz.
Master Clock Frequency: Externally Supplied.
Digital Output Rise Time. Typically 20 ns.
Digital Output Fall Time. Typically 20 ns.
SC1, SC2 to CAL High Setup Time.
SC1, SC2 Hold Time after CAL Goes High.
SLEEP High to CLKIN High Setup Time.
Data Access Time (CS Low to Data Valid).
SCLK Falling Edge to Data Valid Delay (25 ns typ).
MSB Data Setup Time. Typically 380 ns.
SCLK High Pulsewidth. Typically 240 ns.
SCLK Low Pulsewidth. Typically 730 ns.
SCLK Rising Edge to Hi-Z Delay (l/f
CS High to Hi-Z Delay.
Serial Clock Input Frequency.
SCLK Input High Pulsewidth.
SCLK Low Pulsewidth.
Data Access Time (CS Low to Data Valid). Typically 80 ns.
SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
CS High to Hi-Z Delay.
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
CS Setup Time. Typically 20 ns.
Data Delay Time. Typically 90 ns.
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
SS
= DV
SS
= –5 V
10%; AGND = DGND = O V; f
DD
; unless otherwise noted.)
CLKIN
+ 100 ns typ).
CLKIN
=
REV. E