CS44600-CQZ Cirrus Logic Inc, CS44600-CQZ Datasheet - Page 67

• Manufacturer Part Number: CS44600-CQZ
• Description: IC AMP CTLR DGTL 6CH 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Digital Amplifier Controllerr

Specifications of CS44600-CQZ

• Package / Case: 64-LQFP
• Applications: Automotive Systems
• Mounting Type: Surface Mount
• Thd Plus Noise: 0.05 %
• Operating Supply Voltage: 2.5 V
• Supply Current: 150 mA
• Maximum Power Dissipation: 387 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Supply Type: Digital
• Supply Voltage (max): 2.62 V
• Supply Voltage (min): 2.37 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1023 - EVAL BOARD FOR CS44600
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1068-5

DS633F1
7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG)
7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG)
7.30
7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-)
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0])
DISABLE_PWMOUTXX- RESERVED
PWM Minimum Pulse Width Register (address 32h)
er-down state by setting the PDN bit in the register
on page 51
Default = 0
0 - pwm outputs for channel A3 are configured for half-bridge operation
1 - pwm outputs for channel A3 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for only chan-
nel A3. This parameter can only be changed when all modulators and associated logic are in the power
down state by setting the PDN bit in the register
on page 51
Default = 0
0 - pwm outputs for channel B3 are configured for half-bridge operation
1 - pwm outputs for channel B3 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for only chan-
nel B3. This parameter can only be changed when all modulators and associated logic are in the power-
down state by setting the PDN bit in the register
on page 51
7
Default = 0
0 - PWM minus (“-”) differential signal is operational when PWM channel is configured for half-bridge.
1 - PWM minus (“-”) differential signal is disabled when PWM channel is configured for half-bridge.
Function:
Determines if the PWM minus (“-”) differential signal is disabled when the particular PWM channel is con-
figured for half-bridge operation. This bit is ignored for channels configured for full-bridge operation. The
value selected for this bit is applicable to the outputs for all channels configured for half-bridge operation.
This parameter can only be changed when all modulators and associated logic are in the power-down
state by setting the PDN bit in the register
page 51
Default = 00000
Function:
The PWM Minimum Pulse registers allow settings for the minimum allowable pulse width on each of the
PWMOUT differential signal pairs, PWMOUTxx+ and PWMOUTxx-. The value selected in this register is
applicable to all PWM channels. The effective minimum pulse is calculated by multiplying the register val-
ue by the period of the PWM_MCLK. This parameter can only be changed when all modulators and as-
sociated logic are in the power-down state by setting the PDN bit in the register
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
to a ‘1’b. Attempts to write this register while the PDN is not set will be ignored.
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
6
RESERVED MIN_PULSE4 MIN_PULSE3
5
4
“Clock Configuration and Power Control (address 02h)” on
“Clock Configuration and Power Control (address 02h)”
“Clock Configuration and Power Control (address 02h)”
“Clock Configuration and Power Control (address 02h)”
3
MIN_PULSE2
2
MIN_PULSE1
“Clock Configuration and
1
CS44600
MIN_PULSE0
0
67