CS8415A-CZZ Cirrus Logic Inc, CS8415A-CZZ Datasheet - Page 41

• Manufacturer Part Number: CS8415A-CZZ
• Description: IC 96KHZ DGTL RCVR 28-TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Receiverr

Specifications of CS8415A-CZZ

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Audio Control Type: Digital
• Control Interface: I2C, Serial
• Control / Process Application: AV & DVD Receivers, CD-R, Digital Mixing Consoles
• Supply Voltage Range: 2.85V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1122-5

DS470F4
15.APPENDIX C: PLL FILTER
15.1 General
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream.
is a simplified diagram of the PLL in these parts. When the PLL is locked to an AES3 input stream, it is up-
dated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, F
PLL is locked to ILRCK, it is updated at F
There are some applications where low-jitter in the recovered clock, presented on the RMCK pin, is impor-
tant. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown
in
preambles of the AES3 stream to provide lock update information to the PLL. This results in the PLL being
immune to data-dependent jitter affects because the AES3 preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.
If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will
only track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the sample
rate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8415A
clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its
wide lock range mode and re-acquire a new nominal center sample rate.
Figure
INPUT
21,
Figure
and Charge Pump
22,
Comparator
Phase
Figure
÷N
23, and
Figure 18. PLL Block Diagram
Figure
S
so that the duty cycle of the input doesn’t affect jitter.
24. In addition, the PLL has been designed to only use the
C
R
FLT
FLT
C
RIP
VCO
RMCK
CS8415A
S
. When the
Figure 18
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