AD9780 Analog Devices, AD9780 Datasheet - Page 26

• Manufacturer Part Number: AD9780
• Description: Dual 12-Bit, LVDS Interface 500 MSPS DAC
• Manufacturer: Analog Devices

Specifications of AD9780

• Resolution (bits): 12bit
• Dac Update Rate: 500MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9780/AD9781/AD9783
Over temperature, the valid sampling window shifts. Therefore,
when attempting operation of the device over 500 MHz, the
timing must be optimized again whenever the device undergoes
a temperature change of more than 20
in the timing of the digital data port is the propagation delay
variation from the clock output (DCOP/DCON) to the clock
input. If this varies significantly over time (more than 25% of
SET or HLD) due to temperature changes or other effects,
repeat this timing calibration procedure.
At sample rates of ≤400 MSPS, the interface timing margin is
sufficient to allow for a simplified procedure. In this case, the
SEEK bit can be recorded as SMP is swept through the range
from 0 to 31. The center of the first valid sampling window can
then be chosen as the optimal value of SMP. Using the 400 MHz
case from Table 14 as an example, the first valid sampling
window occurs for SMP values of 7 to 13. The center of this
window is 10, so 10 can be used as the optimal SMP value.
DRIVING THE CLK INPUT
The CLK input requires a low jitter differential drive signal. It is
a PMOS input differential pair powered from the 1.8 V supply;
therefore, it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. While these input levels are not directly LVDS-compatible,
CLK can be driven by an offset ac-coupled LVDS signal, as
shown in Figure 59.
If a clean sine clock is available, it can be transformer-coupled
to CLKP and CLKN as shown in Figure 60. Use of a CMOS or
TTL clock is also acceptable for lower sample rates. It can be
routed through a CMOS-to-LVDS translator, and then ac-
Figure 58. Eye Diagram of Data Source Used in Building the 600 MHz Timing
1
CH1
LVDS_N_IN
LVDS_P_IN
100mV
Figure 59. LVDS DAC CLK Drive Circuit
V1: 296mV
V2: –228mV
ΔV: –524mV
Data Array of Table 14
0.1µF
0.1µF
125ps/DIV 2.12ns
20GSPS IT 2.5ps/PT
50Ω
50Ω
o
C. Another consideration
V
CM
= 400mV
A CH1
CLKN
CLKP
58mV
Rev. A | Page 26 of 36
coupled, as described in this section. Alternatively, it can be
transformer-coupled and clamped, as shown in Figure 60.
A simple bias network for generating the 400 mV common-
mode voltage is shown in Figure 61. It is important to use
CVDD18 and CGND for the clock bias circuit. Any noise or
other signal coupled onto the clock is multiplied by the DAC
digital input signal and can degrade the DAC’s performance.
FULL-SCALE CURRENT GENERATION
Internal Reference
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
FS ADJ (Pin 54). A simplified block diagram of the reference
circuitry is shown in Figure 62. The recommended value for
the external resistor is 10 kΩ, which sets up an I
resistor of 120 μA, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear function
of this resistor, a high precision resistor improves gain matching
to the internal matching specification of the devices. Internal
current mirrors provide a current-gain scaling, where I DAC or
Q DAC gain is a 10-bit word in the SPI port register. The default
value for the DAC gain registers gives a full-scale current output
(I
0.1µF
FS
) of approximately 20 mA, where I
I
FS
10kΩ
TTL OR CMOS
FS ADJ
= (86.6 + (0.220 × DAC gain)) × 1000/R
REFIO
CLK INPUT
287Ω
Figure 60. TTL or CMOS DAC CLK Drive Circuit
1kΩ
Figure 61. DAC CLK VCM Generator Circuit
1.2V BAND GAP
AD9783
Figure 62. Reference Circuitry
0.1µF
0.1µF
Q DAC GAIN
I DAC GAIN
CURRENT
SCALING
1nF
FS
1nF
is equal to
50Ω
50Ω
V
CVDD18
CGND
CM
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V
Q DAC
= 400mV
I DAC
CM
DAC FULL-SCALE
REFERENCE CURRENT
= 400mV
REFERENCE
CLKN
CLKP
in the