AD5668 Analog Devices, AD5668 Datasheet - Page 10

• Manufacturer Part Number: AD5668
• Manufacturer: Analog Devices

Specifications of AD5668

• Resolution (bits): 16bit
• Dac Update Rate: 95kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5628/AD5648/AD5668
Table 7. 16-Lead WLCSP Pin Function Descriptions
Pin. No.
B2
A4
B3
B4
B1
C4
C2
D3
D2
C3
C1
D4
D1
A1
A3
A4
Mnemonic
LDAC
SYNC
V
V
V
V
V
V
CLR
V
V
V
V
GND
DIN
SCLK
DD
OUT
OUT
OUT
OUT
REFIN
OUT
OUT
OUT
OUT
A
B
C
D
E
F
G
H
/V
REFOUT
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the next 32 clocks. If SYNC is taken high before the 32
interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR
code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates of up to 50 MHz.
A
D
B
C
BALL A1
INDICATOR
V
V
V
Figure 6. 16-Lead WLCSP
GND
OUT
OUT
OUT
1
Rev. F | Page 10 of 32
(BALL SIDE DOWN)
B
F
H
V
LDAC
Not to Scale
SCL
CLR
OUT
TOP VIEW
2
D
V
V
DIN
V
OUT
REF
3
DD
E
V
V
V
SYNC
OUT
OUT
OUT
4
C
G
A
nd
falling edge, the rising edge of SYNC acts as an
Data Sheet