AD5379 Analog Devices, AD5379 Datasheet
AD5379
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AD5379 Summary of contents
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... REFGND D1 REFGND D2 BUSY AD5379—Protected by U.S. Patent No. 5,969,657. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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... AD5379 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 3 Specifications ..................................................................................... 4 AC Characteristics ........................................................................ 5 Timing Characteristics ..................................................................... 6 Serial Interface .............................................................................. 6 Parallel Interface ........................................................................... 9 Absolute Maximum Ratings .......................................................... 11 ESD Caution ................................................................................ 11 Pin Configuration and Function Descriptions ........................... 12 Terminology .................................................................................... 15 Typical Performance Characteristics ........................................... 16 Functional Description .................................................................. 18 DAC Architecture—General ..................................................... 18 Channel Groups .......................................................................... 18 Transfer Function ....................................................................... 18 V Function ............................................................................. 19 BIAS Reference Selection ...
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... GENERAL DESCRIPTION The AD5379 contains 40 14-bit DACs in one CSPBGA package. The AD5379 provides a bipolar output range determined by the voltages applied to the V (+) and V (−) inputs. The maxi- REF REF mum output voltage span is 17.5 V, corresponding to a bipolar output range of −8. +8.75 V, and is achieved with reference voltages of V (− ...
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... AD5379 SPECIFICATIONS 200 pF to GND kΩ gain = 1; offset = 0 V; all specifications T BIAS L L Table 2. Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error VOUT Temperature Coefficient 2 DC Crosstalk ...
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... Outputs unloaded (typically −16 Σ(V − × Σ(V − V TOTAL DD O SOURCE × θ TOTAL J (−) = −3.5 V; AGND = DGND = REFGND = 0 V; REF ) 1 kHz, V (−) = −1 V BIAS REF (− REF AD5379 ) × SINK ...
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... AD5379 TIMING CHARACTERISTICS SERIAL INTERFACE FIFOEN = 0 V; all specifications T BIAS Table Parameter Limit MIN 4 330 ...
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... VOUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY t 25 RESET t VOUT 19 BUSY Figure 4. Serial Interface Timing Diagram (Standalone Mode DB0 Rev Page AD5379 ...
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... AD5379 SCLK SYNC t 8 DIN D23 INPUT WORD FOR DAC N SDO LDAC BUSY D23' INPUT WORD FOR DAC N D23 UNDEFINED INPUT WORD FOR DAC N Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev Page ...
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... DAC output settling time. ns min CLR pulse width low. ns max CLR / RESET pulse activation time. ns min RESET pulse width low. μs max RESET time indicated by BUSY ), and timed from a voltage level of 1 Rev Page AD5379 (+) = 5 V; REF Table 10 . low. ...
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... AD5379 REG0, REG1, A7–A02 CS WR DB12–DB0 BUSY 1 LDAC VOUT 2 LDAC VOUT CLR VOUT RESET VOUT BUSY LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY ...
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... − −0 − − −0 +0.3 V −40°C to +85°C −65°C to +150°C 150°C 37.5°C/W 8.5°C/W 230°C 10 sec to 40 sec Rev Page AD5379 ...
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... An internal 1 MΩ pull-up device is located on this logic input; therefore, it can be left floating and defaults to a logic high condition. 3 N/C—Do not connect to this pin. Internal active pull-up device on these logic inputs. They default to a logic high condition AD5379 F G TOP VIEW Figure 7 ...
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... Parallel Interface Write Input (Edge Sensitive). The rising edge used in conjunction with CS low and the address bus inputs to write to the selected AD5379 registers. DB13 to DB0 Parallel Data Inputs. The AD5379 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB and DB0 is the LSB Parallel Address Inputs ...
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... MΩ) ensures that the RESET input is held high. The function of this pin is equivalent to that of the power- on reset generator. When this pin is taken low, the AD5379 state machine initiates a reset sequence to digitally reset x1 and x2 registers to their default power-on values. This sequence takes 100 μs (typ). Furthermore, the input to each of the DAC output buffer stages, VOUT0 to VOUT39, is switched to the externally set potential on the relevant REFGND pin ...
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... Output Noise Spectral Density Output noise spectral density is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz measured by loading all DACs to midscale and measuring noise at the output 1/2 measured in nV/(Hz) . Rev Page AD5379 and V terminals are DD SS ...
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... AD5379 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.0 0.5 0 –0.5 –1.0 –1 AD5379 CODE (10 Figure 8. Typical INL Plot 1400 V = +12V –12V SS 1200 V (+) = +5V REF V (–) = –3.5V REF 1000 800 600 400 200 0 –3 –2 –1 0 INL ERROR (LSB) Figure 9. INL Error Distribution (− ...
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... Rev Page 25° +12V –12V SS V OUT V (+) = +5V REF V (–) = –3.5V REF 10V 5mV Figure 17. DAC-to-DAC Crosstalk T = 25° +12V –12V SS V (+) = +5V REF V (–) = –3.5V REF V = +3.3V CC 0.4 0.8 1.2 1.6 2.0 2.4 2.8 INPUT VOLTAGE (V) Figure 18. Supply Current vs. Digital Input Voltage AD5379 3.2 ...
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... The power-on values for the m and c registers are full scale and 0x2000, respectively. The user can individually adjust the voltage range on each DAC channel by overwriting the power-on values of m and c. The AD5379 has digital overflow and underflow detection circuitry to clamp the DAC output at (+) to AGND. This ...
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... If the offset and gain features of the AD5379 are used, then the required output range is slightly different. The chosen output range should take into account the offset and gain errors that need to be trimmed out. Therefore, the chosen output range should be larger than the actual, required range ...
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... LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the x2 registers. However the AD5379 updates the DAC register only if the x2 data has changed, thereby removing unnecessary digital crosstalk. ...
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... All DACs remain in their power-on state until LDAC is used to update the DAC outputs. RESET INPUT FUNCTION The AD5379 can be placed in its power-on reset state at any time by activating the RESET pin. The AD5379 state machine initiates a reset sequence to digitally reset the x1 and x2 registers to their default power-on values. This sequence takes 95 μ ...
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... Special function register DB13 to DB0 Pins The AD5379 accepts a straight, 14-bit parallel word on Pin DB0 to Pin DB13, where Pin DB13 is the MSB and Pin DB0 is the LSB. See Table 12, Table 13, Table 14, Table 15, and Table 16 Pins Each of the 40 DAC channels can be individually addressed. In addition, several channel groupings enable the user to simulta- neously write the same data to multiple DAC channels ...
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... For each AD5379 in the system, 24 clock pulses are required. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD5379 devices in the chain. If fewer than 24 clocks are applied, the write sequence is ignored. When the serial transfer to all devices has been completed, SYNC is taken high ...
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... AD5379 DATA DECODING The AD5379 contains a 14-bit data bus, DB13 to DB0. Depend- ing on the values of REG1 and REG0, this data is loaded into the addressed DAC input register(s), offset (c) register(s), gain (m) register(s), or the special function register. Table 12. DAC Data Format (REG1 = 1, REG0 = 1) ...
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... ADDRESS DECODING The AD5379 contains an 8-bit address bus A0. This address bus allows each DAC input register (x1), each offset (c) register, and each gain (m) register to be individually updated. Table 17. DAC Group Addressing Group All 40 DACs Group A ...
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... AD5379 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5379 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device ...
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... Figure 22 shows the AD5379 as it would be used in an ATE system. Shown here is one pin of a typical logic tester apparent that a number of discrete levels are required for the pin driver, active load circuit, parametric measurement unit, comparators, and clamps ...
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... Temperature Range AD5379ABC −40°C to +85°C AD5379ABCZ 1 −40°C to +85°C 1 EVAL-AD5379EBZ RoHS Compliant Part. ©2004–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 13.00 BSC ...