AD5516 Analog Devices, AD5516 Datasheet

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AD5516

Manufacturer Part Number
AD5516
Description
16-Channel 12-Bit Bipolar Voltage-Output DAC with 14-Bit Increment Mode
Manufacturer
Analog Devices
Datasheet

Specifications of AD5516

Resolution (bits)
14bit
Dac Update Rate
750kSPS
Dac Settling Time
32µs
Max Pos Supply (v)
+13.2V
Single-supply
No
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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*Protected by U.S. Patent No.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FEATURES
High Integration:
14-Bit Resolution via Increment/Decrement Mode
Guaranteed Monotonic
Low Power, SPI
Output Impedance 0.5
Output Voltage Range
Asynchronous Reset Facility (via RESET Pin)
Asynchronous Power-Down Facility (via PD Pin)
Daisy-Chain Mode
Temperature Range: –40 C to +85 C
APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Optical Networks
Industrial Control Systems
Data Acquisition
Low Cost I/O
16-Channel DAC in 12 mm
DSP Compatible
3-Wire Serial Interface
2.5 V (AD5516-1)
5 V (AD5516-2)
10 V (AD5516-3)
®
, QSPI™
DACGND
RESET
5,969,657.
AGND
DGND
BUSY
DCEN
,
MICROWIRE™
SCLK
DV
12 mm CSPBGA
MODE1
CC
CALIBRATION
INTERFACE
AD5516
CONTROL
D
ANALOG
IN
LOGIC
LOOP
D
AV
OUT
,
FUNCTIONAL BLOCK DIAGRAM
CC
and
SYNC
16-Channel, 12-Bit Voltage-Output DAC
7-BIT BUS
MODE2
REF_IN
DAC
DAC
DAC
DAC
GENERAL DESCRIPTION
The AD5516 is a 16-channel, 12-bit voltage-output DAC. The
selected DAC register is written to via the 3-wire serial inter-
face. DAC selection is accomplished via address bits A3–A0.
14-bit resolution can be achieved by fine adjustment in Incre-
ment/Decrement Mode (Mode 2). The serial interface operates
at clock rates up to 20 MHz and is compatible with standard
SPI, MICROWIRE, and DSP interface standards. The output
voltage range is fixed at ± 2.5 V (AD5516-1), ± 5 V (AD5516-2),
and ± 10 V (AD5516-3). Access to the feedback resistor in each
channel is provided via the R
The device is operated with AV
to 5.25 V, V
and requires a stable 3 V reference on REF_IN.
PRODUCT HIGHLIGHTS
1. Sixteen 12-bit DACs in one package, guaranteed monotonic.
2. Available in a 74-lead CSPBGA package with a body size of
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
12 mm
V
BIAS
with 14-Bit Increment Mode
POWER-DOWN
LOGIC
SS
PD
12 mm.
= –4.75 V to –12 V, and V
V
DD
R
R
R
R
OFFS
OFFS
OFFS
OFFS
© 2003 Analog Devices, Inc. All rights reserved.
V
SS
R
R
R
R
FB
FB
FB
FB
FB
0 to R
CC
= 5 V ± 5%, DV
R
V
R
V
R
V
R
V
OUT
FB
OUT
OUT
FB
OUT
FB
FB
FB
0
1
15
14
0
1
14
15
15 pins.
DD
AD5516
= +4.75 V to +12 V,
www.analog.com
CC
= 2.7 V
*

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AD5516 Summary of contents

Page 1

... MHz and is compatible with standard SPI, MICROWIRE, and DSP interface standards. The output voltage range is fixed at ± 2.5 V (AD5516-1), ± (AD5516-2), and ± (AD5516-3). Access to the feedback resistor in each channel is provided via the R The device is operated with ...

Page 2

... Ensure that you do not exceed T . See Absolute Maximum Ratings section. J (MAX With 5 k resistive load, footroom required is as follows: AD5516– AD5516–2, 2.5 V; AD5516– Outputs unloaded. Specifications subject to change without notice +4. +13 2 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. ...

Page 3

... Slew Rate Digital-to-Analog Glitch Impulse Digital Crosstalk Analog Crosstalk AD5516–1 AD5516–2 AD5516–3 Digital Feedthrough Output Noise Spectral Density @ 10 kHz AD5516–1 AD5516–2 AD5516–3 NOTES 1 See Terminology section. 2 Guaranteed by design and characterization; not production tested version: Industrial temperature range –40∞C to +85∞C. ...

Page 4

... AD5516 TIMING DIAGRAMS SCLK SYNC MSB DIN BIT 17 t MODE1 8 BUSY RESET SCLK t MODE2 7 SYNC MSB D BIT OUT t MODE1 8 BUSY Figure 3. Load Circuit for LSB BIT 0 Figure 1. Serial Interface Timing Diagram ...

Page 5

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 6

... AD5516 CSPBGA Ball CSPBGA Number Name Number RESET A3 B7 BUSY DGND B10 B11 OUT SYNC A9 C2 A10 NC C6 A11 NC C10 B1 NC C11 DCEN D10 NC = Not Internally Connected Mnemonic Function AGND (1–2) ...

Page 7

... This is the error in the DAC output voltage with all 1s loaded to the DAC. Ideally the DAC output voltage, with all 1s loaded to the DAC registers, should be 2.5 V – 1 LSB (AD5516-1 – 1 LSB (AD5516-2), and 10 V – 1 LSB (AD5516-3 expressed in LSBs. Negative Full-Scale Error This is the error in the DAC output voltage with all 0s loaded to the DAC ...

Page 8

... CURRENT (mA) TPC 6. V Source and Sink OUT Capability –0.029 REF_IN = 3V NEW –0.030 VALUE CALIBRATION TIME –0.031 OLD VALUE 2.5 s/DIV –0.032 5V BUSY 0V –0.033 TPC 9. AD5516–1 Major Code Transition Glitch Impulse REV. B ...

Page 9

... V (V) OUT TPC 10. AD5516–1 V Repeatability; OUT Programming the Same Code Multiple Times 30 REF_IN = – LSBs TPC 13. Negative Full-Scale Error Distribution REV REF_IN = 3V ...

Page 10

... DAC. BUSY output goes low for the duration of the calibration and further writes to the AD5516 are ignored while BUSY is low. BUSY low time is typically 25 ms. Noise during the calibration (BUSY low period) can result in the selection of a voltage within a ± ...

Page 11

... After the rising edge of SYNC, data is automatically transferred from each device’s input shift register to the addressed DAC. RESET Function The RESET function on the AD5516 can be used to reset all nodes on this device to their power-on reset condition. This is implemented by applying a low going pulse minimum to the RESET Pin on the device ...

Page 12

... PINS OMITTED FOR CLARITY When data transmitted to the DAC, P1.1 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the AD5516 clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 MC68HC11* ...

Page 13

... The power supply lines of the AD5516 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such ...

Page 14

... AD5516 1.70 MAX OUTLINE DIMENSIONS 74-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-74) Dimensions shown in millimeters 12.00 BSC 1.00 TOP VIEW BSC DETAIL A 0.30 MIN 0.70 0.60 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192ABD-1 –14– A1 CORNER INDEX AREA 10.00 BSC BOT TOM ...

Page 15

... Sheet changed from REV REV. A. Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Addition to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to DIGITAL-TO-ANALOG section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Added AD5516 in a High Current Circuit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Added Figure Updated BC-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 REV. B –15– AD5516 Page ...

Page 16

–16– ...

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