AD5335 Analog Devices, AD5335 Datasheet
AD5335
Specifications of AD5335
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AD5335 Summary of contents
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... Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. On the AD5334, AD5335 and AD5336 an asynchronous CLR input is also provided. This resets the contents of the Input Register and the DAC Register to all zeros. These devices also ...
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... See Terminology section. 2 Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095 specifications tested with outputs unloaded. 5 This corresponds to x codes ...
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... LDAC 2 LDAC CLR A0, A1 NOTES Figure 1. Parallel Interface Timing Diagram –3– AD5334/AD5335/AD5336/AD5344 to T MIN MAX Conditions/Comments See Figure 20 REF 1/4 Scale to 3/4 Scale Change ( 1/4 Scale to 3/4 Scale Change (100 H to 300 H) 1/4 Scale to 3/4 Scale Change (100 H to 300 H) 1/4 Scale to 3/4 Scale Change (400 H to C00 H) 1 LSB Change Around Major Carry = 2 V ± ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5334/AD5335/AD5336/AD5344 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Eight Parallel Data Inputs GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V CLR 24 Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. REV. 0 AD5334/AD5335/AD5336/AD5344 V A/B V REF DD AD5334 8-BIT BUFFER V ...
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... DAC 10-BIT BUFFER V DAC 10-BIT BUFFER V DAC 10-BIT BUFFER V DAC TO ALL DACS AND BUFFERS POWER-DOWN LOGIC V C/D PD GND REF AD5335 PIN FUNCTION DESCRIPTIONS is the MSB of these eight bits. 7 –6– AD5335 PIN CONFIGURATION V C/D CLR 1 24 REF V A HBEN REF ...
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... Parallel Data Inputs GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V CLR 28 Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros. REV. 0 AD5334/AD5335/AD5336/AD5344 REF REF DD AD5336 ...
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... AD5334/AD5335/AD5336/AD5344 AD5344 FUNCTIONAL BLOCK DIAGRAM POWER-ON RESET INPUT DAC . . REGISTER . REGISTER . INPUT DAC REGISTER REGISTER WR INTER- FACE A0 LOGIC INPUT DAC A1 REGISTER REGISTER INPUT DAC REGISTER REGISTER LDAC Pin No. Mnemonic Function Unbuffered Reference Input for DAC D. REF Unbuffered Reference Input for DAC C. ...
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... DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illus- trated in Figure 2. ACTUAL OUTPUT VOLTAGE IDEAL DAC CODE Figure 2. Gain Error REV. 0 AD5334/AD5335/AD5336/AD5344 OUTPUT VOLTAGE POSITIVE OFFSET Figure 3. Positive Offset Error and Gain Error OUTPUT VOLTAGE NEGATIVE OFFSET ...
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... AD5334/AD5335/AD5336/AD5344 OFFSET ERROR DRIFT This is a measure of the change in Offset Error with changes in temperature expressed in (ppm of full-scale range)/°C. GAIN ERROR DRIFT This is a measure of the change in Gain Error with changes in temperature expressed in (ppm of full-scale range)/°C. DC POWER-SUPPLY REJECTION RATIO (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage ...
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... CODE Figure 6. AD5335 Typical INL Plot 0 0.4 0.2 0 –0.2 –0.4 –0.6 0 200 400 600 800 1000 CODE Figure 9. AD5335 Typical DNL Plot 0 0 REF MAX INL 0.3 0.2 MAX DNL 0.1 0 –0.1 MIN DNL –0.2 –0.3 MIN INL –0.4 –0.5 40 ...
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... AD5334/AD5335/AD5336/AD5344 0 0 REF 0 GAIN ERROR –0.1 –0.2 –0.3 –0.4 OFFSET ERROR –0.5 –0 – Volts DD Figure 14. Offset Error and Gain Error vs 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V – Figure 17. Supply Current vs. Supply ...
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... The gain of the buffer amplifiers in the AD5334 and AD5336 can be set give an output voltage range The AD5335 and AD5344 have out- REF REF put buffers with unity gain. The devices have a power-down feature that reduces current consumption to only ...
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... High-Byte Enable Input (HBEN) High-Byte Enable is a control input on the AD5335 only that determines if data is written to the high-byte input register or the low-byte input register. The low data byte of the AD5335 consists of data bits data inputs Bits 8 and 9 at data inputs DB ignored during a high byte write. See Figure 30. – ...
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... LOW BYTE DB7 DB6 DB5 DB4 DB3 DB2 X = UNUSED BIT Figure 30. Data Format For AD5335 POWER-ON RESET The AD5334/AD5335/AD5336/AD5344 are provided with a power-on reset function, so that they power defined state. The power-on state is: • Normal operation • 0 – V output range REF • ...
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... Figure 32. AD5336 Data Format for Byte Load with GAIN Data on 8-Bit Bus APPLICATIONS INFORMATION Typical Application Circuits The AD5334/AD5335/AD5336/AD5344 can be used with a wide range of reference voltages and offer full, one-quadrant multiplying capability over a reference range of 0. More typically, these devices may be used with a fixed, preci- sion reference voltage ...
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... Any pair of DACs in the device may be used, but for simplicity the description will refer to DACs A and B. Care must be taken to connect the correct reference inputs to the reference source. The AD5334 and AD5335 have only two reference inputs, V A/B for DACs A and B and V REF DACs C and D ...
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... AD5334/AD5335/AD5336/AD5344 Coarse and Fine Adjustment Using the AD5334/AD5335/ AD5336/AD5344 Two of the DACs in the AD5334/AD5335/AD5336/AD5344 can be paired together to form a coarse and fine adjustment function, as shown in Figure 39. As with the window comparator previ- ously described, the description will refer to DACs A, and B and the reference connections will depend on the actual device used. ...
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... AD5306 8 4 AD5316 10 4 AD5326 12 4 AD5307 8 4 AD5317 10 4 AD5327 12 4 Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html REV. 0 AD5334/AD5335/AD5336/AD5344 Table III. Overview of AD53xx Parallel Devices Pins Settling Time Additional Pin Functions REF BUF 6 µ µs 8 µ µ µs 7 µ µ µs 6 µ ...
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... AD5334/AD5335/AD5336/AD5344 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Thin Shrink Small Outline Package TSSOP (RU-24) 0.311 (7.90) 0.303 (7.70 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25 0.0433 (1.10) MAX 8 0.0256 (0.65) 0.0118 (0.30) 0 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) ...