AD5532 Analog Devices, AD5532 Datasheet

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AD5532

Manufacturer Part Number
AD5532
Description
32-Channel 14-Bit Bipolar Voltage-Output DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD5532

Resolution (bits)
14bit
Dac Update Rate
45kSPS
Dac Settling Time
22µs
Max Pos Supply (v)
+16.5V
Single-supply
No
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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FEATURES
High integration:
Adjustable voltage output range
Guaranteed monotonic
Readback capability
DSP/microcontroller compatible serial interface
Output impedance:
Output voltage span:
Infinite sample-and-hold capability to ±0.018% accuracy
Temperature range −40°C to +85°C
APPLICATIONS
Automatic test equipment
Optical networks
Level setting
Instrumentation
Industrial control systems
Data acquisition
Low cost I/O
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
32-channel DAC in 12 mm × 12 mm CSPBGA
0.5 Ω (AD5532-1, AD5532-2)
500 Ω (AD5532-3)
1 kΩ (AD5532-5)
10 V (AD5532-1, AD5532-3, AD5532-5)
20 V (AD5532-2)
TRACK/RESET
DAC_GND
SER/PAR
AGND
DGND
BUSY
V
IN
AD5532
SCLK D
INTERFACE
CONTROL
LOGIC
DV
ADC
MUX
CC
IN
D
AV
Figure 1. Functional Block Diagram
OUT
CC
REF_IN REF_OUT
SYNC/CS
DAC
DAC
DAC
GENERAL DESCRIPTION
The AD5532
an additional infinite sample-and-hold mode. The selected
DAC register is written to via the 3-wire serial interface; V
for this DAC is then updated to reflect the new contents of the
DAC register. DAC selection is accomplished via Address Bits
A0–A4. The output voltage range is determined by the offset
voltage at the OFFS_IN pin and the gain of the output amplifier.
It is restricted to a range from V
the headroom of the output amplifier.
The device is operated with AV
5.25 V; V
AD5532 requires a stable 3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1.
2.
3.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
ADDRESS INPUT REGISTER
A4–A0
32-channel, 14-bit DAC in one package, guaranteed
monotonic.
Available in a 74-lead CSPBGA package with a body size of
12 mm ×12 mm.
Droopless/infinite sample-and-hold mode.
OFFS_IN
CAL
SS
= −4.75 V to −16.5 V; and V
1
OFFSET_SEL
is a 32-channel, 14-bit voltage-output DAC with
V
DD
© 2010 Analog Devices, Inc. All rights reserved.
V
SS
Voltage-Output DAC
32-Channel, 14-Bit
V
V
OFFS_OUT
WR
OUT
OUT
CC
SS
= 5 V ± 5%; DV
0
31
+ 2 V to V
DD
= 8 V to 16.5 V. The
DD
www.analog.com
– 2 V because of
AD5532
CC
= 2.7 V to
OUT

Related parts for AD5532

AD5532 Summary of contents

Page 1

... OFFS_IN pin and the gain of the output amplifier restricted to a range from V the headroom of the output amplifier. The device is operated with AV 5. AD5532 requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN. PRODUCT HIGHLIGHTS 1. 32-channel, 14-bit DAC in one package, guaranteed monotonic ...

Page 2

... AD5532 TABLE OF CONTENTS Specifications ..................................................................................... 3 ISHA Mode .................................................................................... 5 Timing Characteristics ..................................................................... 6 Parallel Interface ........................................................................... 6 Parallel Interface Timing Diagrams ........................................... 6 Serial Interface .............................................................................. 7 Absolute Maximum Ratings ............................................................ 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Terminology .................................................................................... 11 Dac Mode .................................................................................... 11 ISHA Mode .................................................................................. 11 Typical Performance Characteristics ........................................... 12 Functional Description .................................................................. 14 REVISION HISTORY 6/10—Data Sheet Changed from Rev Rev. D Changes to Table 5 ...

Page 3

... Input Low Voltage Input High Voltage Input Hysteresis (SCLK and CS Only 5.25 V; AGND = DGND = DAC_GND = − All outputs unloaded. All specifications Version AD5532-1/-3/-5 AD5532-2 Only 14 14 ±0.39 ±0.39 ±1 ±1 90/170/250 180/350/500 3.52 7 ±2 ±2 3 ...

Page 4

... Output Noise Spectral Density @ 1 kHz 1 A version: Industrial temperature range -40°C to +85°C; typical at +25°C. 2 See Terminology section. 3 Guaranteed by design and characterization, not production tested. 4 AD780 as reference for the AD5532. 5 Ensure that you do not exceed T (max). See Absolute Maximum Ratings section Output unloaded. 1 ...

Page 5

... A version: Industrial temperature range -40°C to +85°C; typical at +25°C. 2 See Terminology section. 3 Input range 100 Guaranteed by design and characterization, not production tested Version AD5532-2 Only Unit ±0.018 % max ±75 mV max 6.96/7/7.02 min/typ/max max ...

Page 6

... AD5532 TIMING CHARACTERISTICS PARALLEL INTERFACE Table Parameter Limit MIN MAX See Figure 2 and Figure 3, the parallel interface timing diagrams. 2 Guaranteed by design and characterization, not production tested. PARALLEL INTERFACE TIMING DIAGRAMS ...

Page 7

... Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes Figure 5. 24-Bit Write (DAC Mode Figure 6. 14-Bit Read (Both Readback Modes) Rev Page valid OUT high impedance OUT LSB LSB LSB AD5532 ...

Page 8

... J 74-Lead CSPBGA Package, 41°C/W θ Thermal Impedance JA Reflow Soldering Peak Temperature AD5532ABC-x 220°C AD5532ABCZ-x 260°C Time at Peak Temperature 10 sec to 40 sec (150°C − T Max Power Dissipation Max Continuous Load Current 70°C, per Channel Group J 1 Transient currents 100 mA do not cause SCR latch-up ...

Page 9

... AGND2 F11 VO6 G1 VO24 G2 VO8 G10 VO5 G11 VO3 H1 VO23 H2 VIN H10 VO4 H11 VO7 J1 VO22 J2 VO19 Rev Page AD5532 CSPBGA Number Ball Name J10 VO9 J11 VO11 K1 VO17 K2 VO15 K3 VO27 ...

Page 10

... AD5532 Table 7. Pin Function Descriptions Pin Function AGND (1–2) Analog GND pins. AV (1–2) Analog Supply pins. Voltage range from 4. 5. (1–4) V Supply pins. Voltage range from 16 (1–4) V Supply pins. Voltage range from –4. –16.5 V. ...

Page 11

... Gain 1 V OFFS _ IN (ideal expressed in mV and can be positive or OUT ( ( − = × − Full Scale Output Gain . 2 96 Gain input to be acquired the IN AD5532 and transfer OUT = 70 mV. Ideally, mV (actual) OUT ) ) − × OFFS _ IN ...

Page 12

... AD5532 TYPICAL PERFORMANCE CHARACTERISTICS 1 REFIN 0.8 OFFS_IN T = 25°C A 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 10k DAC CODE Figure 10. Typical DNL Plot 1.0 DNL MAX 0.5 INL MAX 0 INL MIN DNL MIN –0.5 –1.0 – TEMPERATURE (°C) Figure 11. INL Error an DNL Error vs. Temperature 5 ...

Page 13

... Figure 17. Acquisition Time and Output Settling Time (ISHA Mode) 70k 60k 50k 40k 30k 20k 10k 2.96 BUSY = 25° REFIN → 1.5V IN 2μs Rev Page 25°C 63791 A V REFIN OFFS_IN 200 0 5.2670 5.2676 5.2682 V (V) OUT Figure 18. ISHA-Mode Repeatability (64 k Acquisitions) AD5532 = 1545 ...

Page 14

... It is important to choose the offset so that V RESET FUNCTION The reset function on the AD5532 can be used to reset all nodes on this device to their power-on reset condition. This is implemented by applying a low-going pulse of between 90 ns and 200 ns to the TRACK / RESET pin on the device. If the applied pulse is less than 90 ns assumed glitch and no operation takes place ...

Page 15

... The output buffer is then switched from the output of the DAC. IN MODES OF OPERATION The AD5532 can be used in four different modes of operation. These modes are set by two mode bits, the first two bits in the serial word. Table 9. Modes of Operation Mode Bit 1 Mode Bit 2 ...

Page 16

... DSPs and microcontrollers. Figure 4, Figure 5, and Figure 6 show the timing diagram for a serial read and write to the AD5532. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers ...

Page 17

... SPORT has been enabled write sequence, data is clocked out on each rising edge of the DSP serial clock and clocked into the AD5532 on the falling edge of its SCLK. In readback, 16 bits of data are clocked out of the AD5532 on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK ignored ...

Page 18

... The AD5532 can be used in many optical networking applications that require a large number of DACs to perform control and measurement functions. In the example shown in Figure 27, the outputs of the AD5532 are amplified and used to control actuators that determine the position of MEMS mirrors in an optical switch. The exact position of each mirror is measured using sensors ...

Page 19

... AD5532 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5532 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device ...

Page 20

... AD5532ABC-3REEL −40°C to +85°C AD5532ABC-5 −40°C to +85°C AD5532ABC-5REEL −40°C to +85°C AD5532ABCZ-1 −40°C to +85°C AD5532ABCZ-1REEL −40°C to +85°C AD5532ABCZ-2 −40°C to +85°C AD5532ABCZ-3 −40°C to +85°C AD5532ABC-5 EVAL-AD5532EBZ RoHS Compliant Part. © ...

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