AD5323 Analog Devices, AD5323 Datasheet - Page 6

• Manufacturer Part Number: AD5323
• Description: 2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5323

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5303/AD5313/AD5323
AC CHARACTERISTICS
V
Table 2.
Parameter
Output Voltage Settling Time
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1
2
3
TIMING CHARACTERISTICS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Guaranteed by design and characterization, not production tested.
See the Terminology section.
Temperature range for Version A and Version B: −40°C to +105°C.
Guaranteed by design and characterization, not production tested.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Figure 4 and Figure 5.
These are measured with the load circuit of Figure 4.
Daisy-chain mode only (see Figure 47).
DD
DD
4, 5
5
5
AD5303
AD5313
AD5323
4, 5
= 2.5 V to 5.5 V; R
= 2.5 V to 5.5 V; all specifications T
2
1, 2, 3
L
= 2 kΩ to GND; C
33
13
13
0
5
4.5
0
100
20
20
20
5
20
0
10
1
Limit at T
(A, B Version)
MIN,
MIN
T
L
MAX
to T
Min
= 200 pF to GND; all specifications T
MAX
, unless otherwise noted.
Typ
6
7
8
0.10
200
0.7
12
0.01
0.01
−70
A, B Version
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
DD
) and timed from a voltage level of (V
Rev. B | Page 6 of 28
Max
8
9
10
3
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK rising edge setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width
SCLK falling edge to LDAC rising edge
CLR pulse width
SCLK falling edge to SDO invalid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
Data setup time
SCLK falling edge to SDO valid
Unit
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
kHz
dB
MIN
to T
Conditions/Comments
V
¼ scale to ¾ scale change (0x40 to 0xc0)
¼ scale to ¾ scale change (0x100 to 0x300)
¼ scale to ¾ scale change (0x400 to 0xc00)
1 LSB change around major carry
(011 . . . 11 to 100 . . . 00)
V
V
IL
REF
REF
REF
+ V
MAX
= V
= 2 V ± 0.1 V p-p, unbuffered mode
= 2.5 V ± 0.1 V p-p, frequency = 10 kHz
IH
)/2.
DD
, unless otherwise noted.
= 5 V