AD7834 Analog Devices, AD7834 Datasheet - Page 15

• Manufacturer Part Number: AD7834
• Description: LC2MOS Quad 14-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7834

• Resolution (bits): 14bit
• Dac Update Rate: 100kSPS
• Dac Settling Time: 10µs
• Max Pos Supply (v): +15.75V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser

When 14-bit transfers are being used, the DAC output voltages,
V
input registers in one of two ways. The first method normally
keeps LDAC high and only pulses LDAC low momentarily to
update all DAC latches simultaneously with the contents of
their respective input registers. The second method ties LDAC
low, and channel updating occurs on a per channel basis after
new data is loaded to an input register.
To avoid the DAC output going to an intermediate value during
a 2-byte transfer, LDAC should not be tied low permanently but
should be held high until the two bytes are written to the input
register. When the selected input register has been loaded with
the two bytes, LDAC should then be pulsed low to update the
DAC latch and, consequently, perform the digital-to-analog
conversion.
In many applications, it may be acceptable to allow the DAC
output to go to an intermediate value during a 2-byte transfer.
In such applications, LDAC can be tied low, thus using one less
control line.
The actual DAC input register that is being written to is deter-
mined by the logic levels present on the device address lines, as
shown in Table 11.
Table 11. AD7835—Address Line Truth Table
A2
0
0
0
0
1
UNIPOLAR CONFIGURATION
Figure 19 shows the AD7834/AD7835 in the unipolar binary
circuit configuration. The V
the
OUT
AD586, a 5 V reference. V
1 to V
A1
0
0
1
1
X
OUT
4, can be updated to reflect new data in the DAC
FOLLOWING 23 BITS OF INFORMATION
PACKAGE ADDRESS MSB, PA4
CONTROL BIT TO USE/IGNORE
PACKAGE ADDRESS LSB, PA0
CHANNEL ADDRESS MSB, D1
X
A0
0
1
0
1
CHANNEL ADDRESS LSB, D2
PACKAGE ADDRESS, PA3
PACKAGE ADDRESS, PA2
PACKAGE ADDRESS, PA1
REF
REF
(+) input of the DAC is driven by
DAC Selected
DAC 1
DAC 2
DAC 3
DAC 4
All DACs selected
(−) is tied to ground. Table 12
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
Figure 18. Bit Assignments for 24-Bit Data Stream of AD7834
NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.
Rev. D | Page 15 of 28
FIRST LEADING ZERO
SECOND LEADING ZERO
MSB, DB13
gives the code table for unipolar operation of the AD7834/
AD7835.
Offset and gain can be adjusted in Figure 19 as follows:
•
•
Many circuits do not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the AD586 can be
left open circuit, and Pin 2 (V
tied to 0 V.
Table 12. Code Table for Unipolar Operation
MSB
11
10
01
00
00
1
2
SECOND MSB, DB12
V
For V
REF
Binary Number in DAC Latch
THIRD MSB, DB11
= V
To adjust offset, disconnect the V
load the DAC with all 0s, and adjust the V
until V
To adjust gain, load the AD7834/AD7835 with all 1s and
adjust R1 until V
REF
1nF
C1
DB10
(+) = 5 V, 1 LSB = 5 V/2
REF
1
ADDITIONAL PINS OMITTED FOR CLARITY
(+); VREF(−) = 0 V for unipolar operation.
1111
0000
1111
0000
0000
DB9
8
OUT
SIGNAL
DB8
AD586
D8
GND
2
= 0 V.
DB7
4
D7
Figure 19. Unipolar 5 V Operation
1111
0000
1111
0000
0000
DB6
D6 D5 D4
5
6
OUT
DB5
R1
10kΩ
= 5 V(16383/16384) = 4.999695 V.
14
DB4
= 5 V/16384 = 305 μV.
LSB
1111
0000
1111
0001
0000
DB3
D3 D2
REF
V
V
REF
REF
THIRD LSB, DB2
+15V
(−)) of the AD7834/AD7835 is
V
AD7834/
AD7835
DD
(+)
(–)
SECOND LSB, DB1
D1 D0
–15V
V
SS
REF
Analog Output (V
V
V
V
V
0 V
LSB, DB0
AD7834/AD7835
+5V
V
AGND
DGND
REF
REF
REF
REF
1
CC
V
(−) input from 0 V,
OUT
(16383/16384) V
(8192/16384) V
(8191/16384) V
(1/16384) V
SIGNAL
REF
GND
1 , 2
(0V TO 5V)
V
(−) voltage
OUT
OUT
)