ADM1065 Analog Devices, ADM1065 Datasheet - Page 5

• Manufacturer Part Number: ADM1065
• Manufacturer: Analog Devices

Specifications of ADM1065

• # Supplies Monitored: 10
• Volt Monitoring Accuracy: 1%
• # Output Drivers: 10
• Fet Drive/enable Output: Both
• Package: 40 ld LFCSP ,48 ld TQFP

Parameter
PROGRAMMABLE DRIVER OUTPUTS
DIGITAL INPUTS (VXx, A0, A1)
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
SERIAL BUS TIMING
SEQUENCING ENGINE TIMING
1
2
3
Specification is not production tested but is supported by characterization data at initial product release.
Timing specifications are guaranteed by design and supported by characterization data.
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
Input Capacitance
Programmable Pull-Down Current,
Input High Voltage, V
Input Low Voltage, V
Output Low Voltage, V
Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Stop Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Input Low Current, I
State Change Time
High Voltage (Charge Pump) Mode
Standard (Digital Output) Mode
Three-State Output Leakage Current
Oscillator Frequency
I
(PDO1 to PDO6)
Output Impedance
V
I
(PDO1 to PDO10)
V
V
I
I
R
I
PULL-DOWN
OUTAVG
OL
SINK
SOURCE
OH
OH
OL
PULL-UP
2
2
(VPx)
2
BUF
LOW
HIGH
3
HD;DAT
HD;STA
SCLK
SU;STA
SU;STO
SU;DAT
IL
IL
F
IL
IH
IL
R
IH
IH
OL
2
Min
11
10.5
2.4
V
0
16
90
2.0
−1
2.0
1.3
0.6
0.6
0.6
1.3
0.6
100
5
PU
− 0.3
Typ
500
12.5
12
20
20
100
5
20
10
Rev. D | Page 5 of 28
Max
14
13.5
4.5
0.50
20
60
29
2
10
110
0.8
1
0.8
0.4
400
300
300
1
kHz
Unit
kΩ
V
V
μA
V
V
V
V
mA
mA
kΩ
mA
μA
V
V
μA
μA
pF
μA
V
V
V
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
μA
μs
Test Conditions/Comments
I
I
2 V < V
V
V
V
I
Maximum sink current per PDO pin
Maximum total sink for all PDO pins
Internal pull-up
Current load on any VPx pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPx pin
V
All on-chip time delays derived from this clock
Maximum V
Maximum V
V
V
VDDCAP = 4.75 V, T
is required
I
V
OH
OH
OL
OUT
PU
PU
PU
PDO
IN
IN
IN
= 20 mA
= 0 μA
= 1 μA
= 5.5 V
= 0 V
= 0 V
(pull-up to VDDCAP or VPx) = 2.7 V, I
to VPx = 6.0 V, I
≤ 2.7 V, I
= −3.0 mA
= 14.4 V
OH
< 7 V
OH
IN
IN
= 5.5 V
= 5.5 V
= 0.5 mA
OH
A
= 25°C if known logic state
= 0 mA
ADM1065
OH
= 0.5 mA