ADUC814 Analog Devices, ADUC814 Datasheet - Page 34

• Manufacturer Part Number: ADUC814
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 6-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC814

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 17
• Adc # Channels: 6

ADuC814
USER INTERFACE TO OTHER ON-CHIP ADuC814 PERIPHERALS
This section gives a brief overview of the various peripherals
also available on-chip. A summary of the SFRs used to control
and configure these peripherals is also given.
DACS
The ADuC814 incorporates two 12-bit, voltage output DACs
on-chip. Each DAC has a rail-to-rail voltage output buffer capa-
ble of driving 10 kΩ/100 pF. They have two selectable ranges,
0 V to V
reference) and 0 V to AV
modes. DAC operation is controlled by a single special function
DACCON
SFR Address
Power-On Default
Bit Addressable
Table 12. DACCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
1
For correct DAC operation on the 2.5 V to V
MODE
REF
Name
MODE
RNG1
RNG0
CLR1
CLR0
SYNC
PD1
PD0
(an external or the internal band gap 2.5 V
RNG1
Description
Mode Select Bit. Selects either 12-bit or 8-bit mode for both DACs.
Set to 1 by the user to enable 8-bit mode (DACxL is the active data register).
Set to 0 by the user to enable 12-bit mode.
DAC1 Output Voltage Range Select Bit.
Set to 1 by the user to configure DAC1 range of 0 V to AV
Set to 0 by the user to configure DAC1 range of 0 V to 2.5 V (V
DAC0 Output Voltage Range Select Bit.
Set to 1 by he user to configure DAC0 range of 0 V to AV
Set to 0 by the user to configure DAC0 range of 0 V to 2.5 V (V
DAC1 Clear Bit.
Set to 1 by the user to enable normal DAC1 operation.
Set to 0 by the user to force DAC1 output voltage to 0 V.
DAC0 Clear Bit.
Set to 1 by the user to enable normal DAC0 operation.
Set to 0 by the user to force DAC0 output voltage to 0 V.
DAC0/1 Update Synchronization Bit.
Set to 1 by the user to enable asynchronous update mode. The DAC outputs update as soon as the DACxL SFRs are
written.
Set to 0 by the user to enable synchronous update mode. The user can simultaneously update both DACs by first
updating the DACxH/L SFRs while SYNC is 0. Both DACs then update simultaneously when the SYNC bit is set to 1.
DAC1 Power-Down Bit.
Set to 1 by the user to power up DAC1.
Set to 0 by the user to power down DAC1.
DAC0 Power-Down Bit.
Set to 1 by the user to power up DAC0.
Set to 0 by the user to power down DAC0.
DD
, and can operate in 12-bit or 8-bit
DAC Control Register
FDH
04H
No
REF
range, the ADC must be powered on.
RNG0
CLR1
Rev. A | Page 34 of 72
(SFR) register, DACCON. Each DAC has two data registers,
DACxH/L. The DAC0 and DAC1 outputs share pins with ADC
inputs ADC4 and ADC5, respectively. When both DACs are on,
the number of analog inputs is reduced to four. Note that in
12-bit mode, the DAC voltage output is updated as soon as the
DACL data SFR has been written; therefore, the DAC data
registers should be updated as DACH first, followed by DACL.
When using the DACs on the V
up the ADC to enable the reference to the DAC section.
See Note 1.
CLR0
DD
DD
.
.
REF
REF
range)
range)
SYNC
1
1
.
.
REF
range it is necessary to power
PD1
PD0