CS3308-CQZ Cirrus Logic Inc, CS3308-CQZ Datasheet - Page 27

• Manufacturer Part Number: CS3308-CQZ
• Description: IC ANLG VOL CTRL 8CH DGTL 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Controllerr

Specifications of CS3308-CQZ

• Package / Case: 48-LQFP
• Applications: High End Audio
• Mounting Type: Surface Mount
• Product: General Purpose Audio Amplifiers
• Output Power: 362 mW
• Available Set Gain: 22 dB
• Thd Plus Noise: - 112 dB
• Operating Supply Voltage: 3.5 V / 5.25 V
• Supply Current: 36 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 2 KOhms
• Input Offset Voltage: 0.75 V
• Input Signal Type: Single
• Minimum Operating Temperature: - 10 C
• Output Signal Type: Analog
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 3.1 V
• Output Type: 8-Channel Audio
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1778 - EVALUATION BOARD FOR CS5376598-1496 - BOARD EVAL FOR CS3308 VOL CTRL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1598

DS702F1
5.9
5.9.1
I²C/SPI Serial Control Formats
The control port is used to access the internal registers of the CS3308
and I²C, with the CS3308 acting as a slave device. SPI Mode is selected if there is a high-to-low transition
on the CS pin after the RESET pin has been brought high. I²C Mode is selected by connecting the CS pin
to VD or DGND.
SDA
I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the CS3308 by the clock,
SCL. The AD0 pin sets the least significant bit of the default chip address and must be connected to VD
or DGND. The AD0 pin is read upon the release of the RESET signal (a low-to-high transition), and its
value (‘0’ when connected to DGND, ‘1’ when connected to VD) is reflected in the LSB of the chip address
in the Individual, Group 1, and Group 2 Chip Address registers.
in I²C Mode.
The signal timings for a read and write cycle are shown in
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low.
The first byte sent to the CS3308 after a Start condition consists of a 7-bit chip address field and a R/W
bit (high for a read, low for a write). To communicate with a CS3308, the chip address field should match
either the Individual, Group 1, or Group 2 device address as set by their respective control port registers.
The eighth bit of the address is the R/W bit. If the read/write bit is set high (indicating a read operation)
and the preceding 7 bits do not match its Individual address, the CS3308 will ignore all traffic on the I²C
bus until a Stop and Start condition occurs.
If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register
to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be
output.
There is a MAP auto-increment capability, enabled by the INCR bit (the MSB of the MAP byte). If INCR
is ‘0’, the MAP will stay constant for successive read or writes. If INCR is ‘1’, the MAP will automatically
increment after each byte is written, allowing block writes of successive registers. Each byte is separated
by an acknowledge (ACK) bit. The ACK bit is output from the CS3308 after each input byte is read and is
input to the CS3308 from the microcontroller after each transmitted byte.
SCL
START
MSB
0
CHIP ADDRESS (WRITE)
1
Chip Address
2
3
4
5
AD0 Connection
LSB
6
Figure 12. Control Port Timing, I²C Write
Table 4. I²C Mode Default Chip Address
7
0
DGND
ACK
8
VD
INCR
9
10 11
6
MAP BYTE
5
12
4
13 14 15
3
Default Chip Address
2
1
16 17 18
0
ACK
1000000b
1000001b
7
Figure 12
19
6
DATA
Table 4
24 25
1
0
ACK
.
26
The control port has 2 modes: SPI
and
27 28
shows the default chip addresses
7
DATA +1
Figure
6
1
0
13. A Start condition is
7
DATA +n
6
1
0
CS3308
ACK
STOP
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