ADP130 Analog Devices, ADP130 Datasheet - Page 5

• Manufacturer Part Number: ADP130
• Description: 350 mA, Low VIN, Low Quiescent Current, CMOS Linear Regulator
• Manufacturer: Analog Devices

ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VBIAS to GND
EN to GND
VOUT to GND
Storage Temperature Range
Operating Temperature Range
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec)
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in combi-
nation. The ADP130 may be damaged when junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can exceed
the maximum limit as long as the junction temperature is within
specification limits. The junction temperature (T
is dependent on the ambient temperature (T
dissipation of the device (P
resistance of the package (θ
following formula:
T
J
= T
A
+ (P
D
× θ
JA
)
D
), and the junction-to-ambient thermal
JA
). T
J
is calculated using the
A
), the power
Rating
−0.3 V to +3.6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +125°C
125°C
300°C
J
) of the device
Rev. B | Page 5 of 20
The junction-to-ambient thermal resistance (θ
is based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The specified
values of θ
For details about board construction, refer to JEDEC JESD51-7.
Ψ
with units of °C/W. Ψ
calculation using a four-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. Ψ
power flowing through multiple thermal paths rather than a single
path, as in thermal resistance (θ
include convection from the top of the package as well as radiation
from the package, factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
the following formula:
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about Ψ
THERMAL RESISTANCE
θ
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
ESD CAUTION
JA
JB
and Ψ
is the junction-to-board thermal characterization parameter
T
J
= T
JB
JA
B
are specified for the worst-case conditions, that is, a
+ (P
are based on a four-layer, 4 in × 3 in circuit board.
D
× Ψ
JB
JB
)
of the package is based on modeling and
θ
170
B
) and power dissipation (P
JA
JB
). Therefore, Ψ
JB
.
JB
JB
JA
measures the component
more useful in real world
may vary, depending on
Ψ
43
JB
JA
J
) is calculated
) of the package
JB
thermal paths
ADP130
Unit
°C/W
D
), using