MAX13326GUI/V+ Maxim Integrated Products, MAX13326GUI/V+ Datasheet - Page 16

• Manufacturer Part Number: MAX13326GUI/V+
• Description: IC AUD LINE DVR DL AUTO 28TSSOP
• Manufacturer: Maxim Integrated Products
• Type: Line Driver, Transmitterr

Specifications of MAX13326GUI/V+

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Number Of Channels Per Chip: 2
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface: I2C
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 2 / 2
• Output Current: 580 mA
• Output Voltage: +/- 0.2 mV
• Supply Current: 1.7 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual Automotive, Audio Line Drivers
with I
Table 17. Overvoltage Diagnostic
Writing to the MAX13325/MAX13326 using I
that first the master sends a START (S) condition fol-
lowed by the device’s I
the master sends the register address of the register
that is to be programmed. The master then ends com-
munication by issuing a STOP (P) condition to relinquish
Figure 1. I
Figure 2. Bit Transfer
16
FAULT CONDITION
_____________________________________________________________________________________
Overvoltage
SDA
SCL
Shutdown
2
t
F
C Timing
S
2
Applications Information
C Control and Diagnostic
t
HD:STA
t
LOW
2
DUMP bit is set in the GFAULT
C address. After the address,
Left and right channels switch
FLAG bit set. See Table 7.
off and output goes to a
high-impedance state.
FLAG is asserted low.
register. See Table 4.
t
LOW
STATUS REPORT
t
HD:DAT
SDA
SCL
t
SU:DAT
Serial Interface
t
HIGH
DATA VALID
DATA LINE
STABLE;
2
C requires
t
F
t
SU:STA
DATA ALLOWED
CHANGE OF
In GMASK register, set
Cannot be masked.
S
MDUMP bit to 1.
control of the bus, or a Repeated START (Sr) condition to
communicate to another I
Each SCL rising edge transfers one data bit. The data
on SDA must remain stable during the high portion of the
SCL clock pulse (see Figure 2). Changes in SDA while
SCL is high are read as control signals (see the START
and STOP Conditions section). When the serial interface
is inactive, SDA and SCL idle high.
r
See Table 8.
UNMASK
t
HD:STA
t
SP
t
SU:STO
V
the RETRYL bit to 1. Right channel
threshold. Cleared on reading the
Left channel is enabled by setting
is enabled by setting the RETRYR
DD
GFAULT register. Note: 500ms
autoretry in stand-alone mode.
2
t
C slave (see Figure 1).
R
voltage falls below overvoltage
bit to 1. See Table 3.
P
RECOVERY
t
BUF
S
Bit Transfer