TEF6892H/V3,557 NXP Semiconductors, TEF6892H/V3,557 Datasheet - Page 31

• Manufacturer Part Number: TEF6892H/V3,557
• Description: IC RADIO SIGNAL PROC 44-QFP
• Manufacturer: NXP Semiconductors
• Type: Car Signal Processorr

Specifications of TEF6892H/V3,557

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282868557; TEF6892H/V3; TEF6892H/V3

Philips Semiconductors
Table 36 Description of data byte 2H
Table 37 RDS clock description
11.2.4
Table 38 Format of data byte 3H with default setting
Table 39 Description of data byte 3H
Table 40 Description of data available control
2003 Oct 21
Car radio integrated signal processor
7 and 6
7 and 6
CLKO
DAC1
DAC1
5 to 2
BIT 7
4 to 0
BIT
BIT
1
0
0
0
1
1
0
5
0
0
1
1
S
UBADDRESS
SYMBOL
SYMBOL
BBG[4:0]
DAC[1:0]
TST[3:0]
NWSY
CLKO
DAC0
DAC0
BIT 6
CLKI
CLKI
0
1
0
1
0
0
1
0
1
3H; RDS CONTROL
Not used. Set to logic 0.
Test. TST[3:0] = 0000: normal operation.
Clock input or output and buffered or unbuffered raw RDS output. See Table 37.
RDS decoder mode; pin RDCL is disabled
for RDS decoder bypass mode; RDCL is burst clock input for raw RDS read-out
for RDS decoder mode: continuous block rate data available signal at pin RDCL;
for RDS decoder bypass mode: RDCL is clock output for raw RDS read-out
reserved
Data available control. See Table 40.
New synchronization search. 0 = synchronization is started by BBL value of bad block
counter only; 1 = restart of synchronization search. NWSY is automatically reset to
logic 0.
Maximum bad blocks gain. Number of invalid blocks (bad block counter) that is
allowed during synchronization search. If reached, a new synchronization is started.
BBG[4:0] = 0 disables this function.
standard output mode; new block data is signalled at every new received block
fast PI search mode; during synchronization search (SYNC = 0) A or C’ block data is
available and signalled, when synchronized standard output mode is active
reduced data request mode; when synchronized new block data is signalled every two
new received blocks
decoder bypass mode; raw RDS data from demodulator is available on pin RDDA
NWSY
BIT 5
0
BBG4
BIT 4
0
31
DATA AVAILABLE CONTROL
BBG3
RDS/RBDS CLOCK
BIT 3
0
DESCRIPTION
DESCRIPTION
BBG2
BIT 2
0
BBG1
BIT 1
0
Product specification
TEF6892H
BBG0
BIT 0
0