TDA7309 STMicroelectronics, TDA7309 Datasheet - Page 6

• Manufacturer Part Number: TDA7309
• Description: IC PROCESSOR STER/AUDIO 20-PDIP
• Manufacturer: STMicroelectronics
• Type: Audio Processorr

Specifications of TDA7309

• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -

TDA7309
2
3
I
C BUS INTERFACE
2
Data transmission from microprocessor to the TDA7313 and viceversa takes place thru the 2 wires I
C
BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must
be connected).
3.1 Data Validity
As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2 Start and Stop Conditions
As shown in fig. 16 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
3.4 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
17). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
3.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data. This approach of
course is less protected from misworking and decreases the noise immunity.
2
Figure 15. Data Validity on the I
CBUS
SDA
SCL
DATA LINE
CHANGE
STABLE, DATA
DATA
VALID
ALLOWED
D99AU1031
2
Figure 16. Timing Diagram of I
CBUS
SCL
2
I
CBUS
SDA
D99AU1032
START
STOP
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