TDA7460ND STMicroelectronics, TDA7460ND Datasheet - Page 30

IC PROCESSOR CAR RAD SGNL SO-20

TDA7460ND

Manufacturer Part Number
TDA7460ND
Description
IC PROCESSOR CAR RAD SGNL SO-20
Manufacturer
STMicroelectronics
Type
Car Signal Processorr
Datasheet

Specifications of TDA7460ND

Applications
Automotive Systems
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Stereo decoder part
5.5.9
5.6
30/49
The gain can be programmed through 4 bits in the "Stereo decoder-Adjustment" byte.
The mono voltage VMO (0 dB channel separation) can be chosen selecting 33, 42, 50 or
58 % of REF5V.All necessary internal reference voltages like REF5V are derived from a
bandgap circuit. Therefore they have a temperature coefficient near zero. This is useful if the
fieldstrength signal is also temperature compensated.
But most if devices apply a level voltage with a TC of 3300 ppm. The TDA7460ND offers this
TC for the reference voltages, too. The TC is selectable with bit D7 of the "stereo decoder
adjustment" byte.
Figure 24. Relation between internal and external LEVEL voltage and setup of stereo
High cut control
The high cut control setup is similar to the stereo blend control setup: the starting point
VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5 V whereas the range can be
set to be 17 or 33% of VHCH (see
Figure 25. High cut characteristics
Functional description of the noise blanker
In the automotive environment the MPX signal is disturbed by spikes produced by the
ignition and for example the wiper motor. The aim of the noise blanker part is to cancel the
audible influence of the spikes. Therefore the output of the stereo decoder is held at the
actual voltage for 40 μs.
In a first stage the spikes must be detected but to avoid a wrong triggering on high
frequency (white) noise a complex trigger control is implemented. Behind the trigger stage a
pulse former generates the "blanking" pulse. To avoid any crosstalk to the signal path the
noise blanker is supplied by his own biasing circuit.
VOLTAGES
INTERNAL
REF 5V
VSBL
blend
VMO
SETUP OF VST
TIME CONSTANT
VST
LOWPASS
3
τ
τ
Deemp
Deemp
LEVEL
FIELDSTRENGHT VOLTAGE
Figure
t
LEVEL INTERN
VHCL
25.).
D97AU640
VSBL
VOLTAGES
INTERNAL
REF 5V
58%
50%
42%
33%
D97AU639
VHCH
FIELDSTRENGHT
SETUP OF VMO
VMO
VST
LEVEL INTERN
FIELDSTRENGHT VOLTAGE
t
TDA7460ND

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