EP4SGX180FF35C3 Altera Corporation, EP4SGX180FF35C3 Datasheet - Page 72

no-image

EP4SGX180FF35C3

Manufacturer Part Number
EP4SGX180FF35C3
Description
IC STRATIX IV FPGA 180K 1152FBGA
Manufacturer
Altera Corporation
Series
Stratix® IV GXr
Datasheet

Specifications of EP4SGX180FF35C3

Number Of Logic Elements/cells
175750
Number Of Labs/clbs
7030
Total Ram Bits
13954048
Number Of I /o
564
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA
Lead Free Status
Contains lead
Rohs Status
RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4SGX180FF35C3
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP4SGX180FF35C3
Manufacturer:
ALTERA
0
Part Number:
EP4SGX180FF35C3G
0
Part Number:
EP4SGX180FF35C3N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP4SGX180FF35C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP4SGX180FF35C3N
Manufacturer:
ALTERA
0
Part Number:
EP4SGX180FF35C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP4SGX180FF35C3N
0
1–64
Table 1–53. Glossary Table (Part 2 of 4)
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
M, N, O
Letter
K, L,
P
Q
R
J
J
JTAG Timing
Specifications
PLL
Specifications
R
L
Subject
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
Diagram of PLL Specifications
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Receiver differential input discrete resistor (external to Stratix IV device).
TMS
TDO
TCK
TDI
Core Clock
Key
CLK
Reconfigurable in User Mode
t
JCH
t
JPZX
t
JCP
t
JCL
Switchover
f
IN
External Feedback
N
t
JPCO
f
INPFD
(1)
t
JPSU
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
PFD
M
Definitions
CP
t
LF
JPH
VCO
f
VCO
t
JPXZ
Counters
C0..C9
December 2011 Altera Corporation
CLKOUT Pins
f
f
OUT_EXT
OUT
GCLK
RCLK
Glossary

Related parts for EP4SGX180FF35C3