STR911FAW47 STMicroelectronics, STR911FAW47 Datasheet - Page 18

• Manufacturer Part Number: STR911FAW47
• Description: ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR911FAW47

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

Functional overview
3.9
3.9.1
3.9.2
Note:
3.9.3
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Vectored interrupt controller (VIC)
Interrupt management in the STR91xFA is implemented from daisy-chaining two standard
ARM VIC units. This combined VIC has 32 prioritized interrupt request channels and
generates two interrupt output signals to the CPU. The output signals are FIQ and IRQ, with
FIQ having higher priority.
FIQ handling
FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an
Interrupt Service Routine (ISR) directly without having to determine/prioritize the interrupt
source, minimizing ISR latency. Typically only one interrupt source is assigned to FIQ. An
FIQ interrupt has its own set of banked registers to minimize the time to make a context
switch. Any of the 32 interrupt request input signals coming into the VIC can be assigned to
FIQ.
IRQ handling
IRQ is a vectored interrupt and is the logical OR of all 32 interrupt request signals coming
into the 32 IRQ channels. Priority of individual vectored interrupt requests is determined by
hardware (IRQ channel Intr 0 is highest priority, IRQ channel Intr 31 is lowest).
However, inside the same VIC (primary or secondary VIC), CPU firmware may re-assign
individual interrupt sources to individual hardware IRQ channels, meaning that firmware can
effectively change interrupt priority levels as needed within the same VIC (from priority 0 to
priority 16).
VIC0 (primary VIC) interrupts always have higher priority than VIC1 (secondary VIC)
interrupts
When the IRQ signal is activated by an interrupt request, VIC hardware will resolve the IRQ
interrupt priority, then the ISR reads the VIC to determine both the interrupt source and the
vector address to jump to the service code.
The STR91xFA has a feature to reduce ISR response time for IRQ interrupts. Typically, it
requires two memory accesses to read the interrupt vector address from the VIC, but the
STR91xFA reduces this to a single access by adding a 16th entry in the instruction branch
cache, dedicated for interrupts. This 16th cache entry always holds the instruction that reads
the interrupt vector address from the VIC, eliminating one of the memory accesses typically
required in traditional ARM implementations.
Interrupt sources
The 32 interrupt request signals coming into the VIC on 32 IRQ channels are from various
sources; 5 from a wake-up unit and the remaining 27 come from internal sources on the
STR91xFA such as on-chip peripherals, see
interrupt on any IRQ channel.
One of the 5 interrupt requests generated by the wake-up unit (IRQ25 in
from the logical OR of all 32 inputs to the wake-up unit. Any of these 32 inputs may be used
to wake up the CPU and cause an interrupt. These 32 inputs consist of 30 external
interrupts on selected and enabled GPIO pins, plus the RTC interrupt, and the USB Resume
interrupt.
Doc ID 13495 Rev 6
Table
6. Optionally, firmware may force an
Table
STR91xFAxxx
6) is derived