ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 131

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

ST10F273Z4
Table 65.
1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
2. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,
3. Consult your vendor to know which version of the on-chip oscillator amplifier is enabled (Low-Power or Wide-Swing).
4. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
5. The maximum current may be drawn while the respective signal line remains inactive.
6. The minimum current must be drawn in order to drive the respective signal line active.
7. The power supply current is a function of the operating frequency (f
8. Not 100% tested, guaranteed by design characterization.
9. The Idle mode supply current is a function of the operating frequency (f
10. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at V
11. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the
I
I
I
I
I
PD2
PD3
SB1
SB2
SB3
Symbol
and the voltage is imposed by the external circuitry.
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next
circuitry.
for CS output and the open drain function is not enabled.
illustrated in the
disconnected and all inputs at V
doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules (for ICC1)
Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM (for ICC2)
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
illustrated in the Figure 36 below. These parameters are tested and at maximum CPU clock with all outputs disconnected
and all inputs at V
– 0.1 V to V
Regulator is assumed off: in case it is not, additional 1mA shall be assumed. The value for this parameter shall be
considered as “Target Value” to be confirmed by silicon characterization.
specified range (i.e. V
not exceed 50mA. The supply voltage must remain within the specified limits.
Power down supply current
(RTC on, main oscillator on,
main voltage regulator off)
Power down supply current
(RTC on, 32 kHz oscillator on,
main voltage regulator off)
Stand-by supply current
(RTC off, oscillators off, V
Stand-by supply current
(RTC on, 32kHz oscillator on, main V
V
Stand-by supply current
(V
STBY
DD
DC characteristics (continued)
DD
, V
transient condition)
Figure 36
AREF
on)
IL
or V
OV
= 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
IH
> V
, RSTIN pin at V
below. This parameter is tested at V
DD
Parameter
+ 0.3 V or V
IL
or V
(10)
(10)
(10)(8)
IH
DD
, RSTIN pin at V
(10) (11)
(10)
off, V
IH1Min.
OV
< –0.3 V). The absolute sum of input overload currents on all port pins may
STBY
DD
on)
off,
IH1min
DDmax
: this implies I/O current is not considered. The device is
T
T
V
T
V
T
V
T
V
T
–
CPU
A
A
A
A
A
A
STBY
STBY
STBY
STBY
and at maximum CPU clock frequency with all outputs
Test condition
= 25 °C
= 25 °C
= T
= T
= 25 °C
= 125 °C
CPU
is expressed in MHz). This dependency is
J
J
= 5.5 V
= 5.5 V
= 5.5 V
= 5.5 V
= 25 °C
= 125 °C
is expressed in MHz). This dependency is
Figure 35
for a scheme of the input
Electrical characteristics
Min.
–
–
–
–
–
–
–
Limit values
Max.
250
500
250
500
1.1
2.5
8
131/188
DD
Unit
mA
mA
mA
µA
µA
µA
µA