ST7MC1K4 STMicroelectronics, ST7MC1K4 Datasheet - Page 50

• Manufacturer Part Number: ST7MC1K4
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC1K4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
8 POWER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see
halt and Halt.
After a RESET the normal operating mode is se-
lected by default (Run mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
(f
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 25. Power Saving Mode Transitions
50/309
1
OSC2
Figure
).
ACTIVE HALT
25): Slow, Wait (Slow-wait), Active-
SLOW WAIT
POWER CONSUMPTION
SLOW
HALT
WAIT
RUN
Low
High
8.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
– To adapt the internal clock frequency (f
Slow mode is controlled by three bits in the MCC-
SR register: the SMS bit which enables or disables
Slow mode and two CPx bits which select the in-
ternal slow frequency (f
In this mode, the master clock frequency (f
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
(f
Note: Slow-wait mode is activated when entering
the Wait mode while the device is already in Slow
mode.
Figure 26. Slow Mode Clock Transitions
CPU
internal clock in the device,
the available supply voltage.
).
CP1:0
SMS
f
CPU
f
OSC2
f
FREQUENCY
OSC2
00
NEW SLOW
REQUEST
/2
CPU
01
).
f
OSC2
NORMAL RUN MODE
/4
REQUEST
CPU
f
OSC2
OSC2
) to
)