ST72324BK6-Auto STMicroelectronics, ST72324BK6-Auto Datasheet - Page 106

• Manufacturer Part Number: ST72324BK6-Auto
• Description: 8-bit MCU for automotive, 3.8 to 5.5V operating range with 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST72324BK6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and external clock input
• 4 Power Saving Modes: Slow, Wait, Active Halt, and Halt

On-chip peripherals
10.4.8
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SPI registers
SPI Control Register (SPICR)
Table 55.
SPICR
Bit
7
6
5
4
3
SPIE
R/W
7
MSTR
Name
CPOL
SPR2
SPIE
SPE
SPICR register description
SPE
R/W
Serial Peripheral Interrupt Enable
Serial Peripheral Output Enable
Divider Enable
Master mode
Clock Polarity
6
This bit is set and cleared by software.
0: Interrupt is inhibited.
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
is cleared by reset, so the SPI peripheral is not initially connected to the external
pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
and the functions of the MISO and MOSI pins are reversed.
This bit is set and cleared by software. This bit determines the idle state of the
serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
SPR2
R/W
5
Doc ID13466 Rev 4
MSTR
R/W
4
Master mode fault (MODF) on page
Master mode fault (MODF) on page
CPOL
Function
R/W
3
Table 56: SPI master mode SCK
CPHA
R/W
2
Reset value: 0000 xxxx (0xh)
1
103). The SPE bit
103).
ST72324B-Auto
SPR[1:0]
R/W
0