ST72561AR7 STMicroelectronics, ST72561AR7 Datasheet - Page 21

• Manufacturer Part Number: ST72561AR7
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72561AR7

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example, in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
For more details, refer to dedicated parametric
section.
Main features
■
■
■
■
Figure 11. Clock, Reset and Supply Block Diagram
RESET
OSC2
OSC1
– 4 Crystal/Ceramic resonator oscillators
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
V
V
Optional PLL for multiplying the frequency by 2
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
System Integrity Management (SI)
SS
DD
capability for monitoring the main supply
OSCILLATOR
RESET SEQUENCE
Figure
MULTI-
(MO)
MANAGER
(RSM)
11.
f
OSC
(option)
PLL
f
OSC2
SICSR
SYSTEM INTEGRITY MANAGEMENT
0
AVD AVD LVD
IE
AVD Interrupt Request
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required.
“PLL Characteristics” on page 228.
Figure 10. PLL Block Diagram
AUXILIARY VOLTAGE
F
LOW VOLTAGE
f
RF
OSC
DETECTOR
DETECTOR
(AVD)
(LVD)
0
/ 8000
0
PLL x 2
0
OSC2
/ 2
WDG
RF
= f
OSC
CLOCK (MCC/RTC)
WITH REALTIME
PLL OPTION BIT
TIMER (WDG)
CONTROLLER
MAIN CLOCK
WATCHDOG
/2.
8-BIT TIMER
0
1
OSC2
ST72561
of 4 to 8
f
OSC2
21/265
f
See
CPU