ST72324LS4 STMicroelectronics, ST72324LS4 Datasheet - Page 72

• Manufacturer Part Number: ST72324LS4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72324LS4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Lxx
16-BIT TIMER (Cont’d)
Table 18. 16-Bit Timer Register Map and Reset Values
1
2
3
4
72/154
1
Timer A: 3E
Timer A: 3C
Timer A: 3D
Timer A: 3F
Timer B: 4E
Timer A: 3A
Timer B: 4A
Timer A: 3B
Timer B: 4B
Timer B: 4C
Timer B: 4D
In Flash devices, these bits are not used in Timer A and must be kept cleared.
In Flash devices, the TAOC2HR and TAOC2LR Registers are write only, reading them will return unde-
Timer A: 32
Timer B: 42
Timer A: 31
Timer B: 41
Timer A: 33
Timer B: 43
Timer A: 34
Timer B: 44
Timer A: 35
Timer B: 45
Timer A: 36
Timer B: 46
Timer A: 37
Timer B: 47
Timer B: 4F
Timer A: 38
Timer B: 48
Timer A: 39
Timer B: 49
In Flash devices, these bits are forced by hardware to 0 in Timer A
In Flash devices, the TAIC2HR and TAIC2LR registers are not present.
fined values
Address
(Hex.)
3
3
4
4
CR1
Reset Value
CR2
Reset Value
CSR
Reset Value
IC1HR
Reset Value
IC1LR
Reset Value
OC1HR
Reset Value
OC1LR
Reset Value
OC2HR
Reset Value
OC2LR
Reset Value
CHR
Reset Value
CLR
Reset Value
ACHR
Reset Value
ACLR
Reset Value
IC2HR
Reset Value
IC2LR
Reset Value
Register
Label
OC1E
ICF1
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
ICIE
7
0
0
1
0
1
0
1
1
1
1
x
x
x
x
x
OC2E
OCF1
OCIE
6
0
0
x
x
x
0
0
0
0
1
1
1
1
x
x
1
TOIE
OPM
TOF
5
0
0
x
x
x
0
0
0
0
1
1
1
1
x
x
FOLV2
ICF2
PWM
4
0
0
x
x
x
0
0
0
0
1
1
x
x
1
1
2
1
FOLV1
OCF2
CC1
3
0
0
x
x
x
0
0
0
0
1
1
x
x
1
1
2
OLVL2
TIMD
CC0
2
0
0
0
0
0
0
0
1
1
x
x
x
x
1
1
IEDG2
IEDG1
1
0
0
0
0
0
0
1
0
0
x
x
x
x
x
-
1
1
EXEDG
OLVL1
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
0
0
0
x
x
x
0
0
0
0
1
0
1
0
x
x
-