ST72325S6 STMicroelectronics, ST72325S6 Datasheet - Page 38

• Manufacturer Part Number: ST72325S6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72325S6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72325xx
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 23. Concurrent Interrupt Management
Figure 24. Nested Interrupt Management
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11 / 10
11 / 10
MAIN
MAIN
Figure
RIM
RIM
22.
IT2
IT2
IT1
IT1
IT4
TRAP
TRAP
IT1
IT4
IT0
IT0
7.4 CONCURRENT & NESTED MANAGEMENT
The following
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
IT3
IT3
IT1
24. The interrupt hardware priority is given
IT4
IT2
Figure 23
10
10
SOFTWARE
PRIORITY
LEVEL
SOFTWARE
PRIORITY
LEVEL
MAIN
MAIN
and
3
3
3
3
3
3
3/0
3
3
2
1
3
3
3/0
Figure 24
I1
I1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 0
0 1
1 1
1 1
show two
I0
I0