ST72361K6 STMicroelectronics, ST72361K6 Datasheet - Page 39

• Manufacturer Part Number: ST72361K6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72361K6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

POWER SAVING MODES (Cont’d)
8.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see
tails on the MCCSR register) and when the
AWUEN bit in the AWUCSR register is cleared.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
Mapping,” on page
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see
ure
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’ to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 10.1 on page 52
Figure 25. HALT Timing Overview
[MCCSR.OIE=0]
INSTRUCTION
RUN
26).
HALT
HALT
Section 10.2 on page 58
256 OR 4096 CPU
33) or a RESET. When exiting
CYCLE DELAY
INTERRUPT
RESET
OR
for more details).
Table 9, “Interrupt
VECTOR
FETCH
for more de-
RUN
Fig-
Figure 26. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
N
WATCHDOG
WDGHALT
(MCCSR.OIE=0)
Table 9, “Interrupt Mapping,” on page 33
RESET
1
INTERRUPT
Y
1)
ENABLE
3)
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
CPU
I[1:0] BITS
CPU
I[1:0] BITS
N
CYCLE
RESET
Y
WATCHDOG
DELAY
DISABLE
2)
ST72361
XX
XX
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
10
39/225
4)
4)
for