ST72264G2 STMicroelectronics, ST72264G2 Datasheet - Page 151

• Manufacturer Part Number: ST72264G2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72264G2

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 91. RESET pin protection when LVD is enabled.
Figure 92. RESET pin protection when LVD is disabled.
Note 1:
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
Note 5: Please refer to
Required
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
– 1. Check that all recommendations related to the reset circuit have been applied (see notes above).
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
EXTERNAL
EXTERNAL
CIRCUIT
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
below the V
internally.
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
Section 13.2.2 on page
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
RESET
USER
Recommended for EMC
RESET
Required
IL
V
max. level specified in
DD
0.01µF
0.01µF
0.01µF
“Illegal Opcode Reset” on page 123
127.
1MΩ
Optional
(note 3)
V
DD
Section 13.9.1 on page
4.7kΩ
V
V
DD
DD
R
R
for more details on illegal opcode reset conditions.
ON
ON
Filter
Filter
150. Otherwise the reset will not be taken into account
1)2)3)4)
1)
GENERATOR
ST72260Gx, ST72262Gx, ST72264Gx
PULSE
GENERATOR
PULSE
WATCHDOG
ILLEGAL OPCODE
WATCHDOG
ILLEGAL OPCODE
LVD RESET
INTERNAL
RESET
INTERNAL
RESET
INJ(RESET)
ST72XXX
ST72XXX
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5)
5)
in