LNBH24 STMicroelectronics, LNBH24 Datasheet

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LNBH24

Manufacturer Part Number
LNBH24
Description
Dual LNB supply and control IC with step-up and I2C interface
Manufacturer
STMicroelectronics
Datasheet

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Features
Description
Intended for analog and digital dual satellite
receivers/sat-TV, sat-PC cards, the LNBH24 is a
monolithic voltage regulator and interface IC,
assembled in PowerSSO-36 ePad, specifically
Table 1.
April 2009
Complete interface between LNBS and I²C bus
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93%@0.5 A)
Selectable output current limit through external
resistor
Compliant with main satellite receivers output
voltage specification
New accurate built-in 22 kHz tone generator
meets widely accepted standards (patent
pending)
Fast oscillator start-up facilitates DiSEqC™
encoding
Built-in 22 kHz tone detector supports bi-
directional DiSEqC™ 2.0
Very low-drop post regulator and high
efficiency step-up PWM with integrated power
N-MOS allow low power losses
Two output pins suitable for bypassing the
output R-L filter and avoiding tone distortion (R-
L filter as per DiSEqC™ 2.0 specs, see typ.
application circuits)
Overload and over-temperature internal
protections with I²C diagnostic bits
Output voltage and output current level
diagnostic feedback by I²C bits
LNB short circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
Dual LNB supply and control IC with step-up and I²C interface
LNBH24PPR
Order code
Device summary
PowerSSO-36 (Exposed pad)
Package
Rev 3
designed to provide the 13/18 V power supply and
the 22 kHz tone signalling for two independent
LNB down-converters in the antenna dishes
and/or multi-switch box. In this application field, it
offers a dual tuner STBs with extremely low
component count, low power dissipation together
with simple design and I²C standard interfacing.
PowerSSO-36 (ePad)
Tape and reel
Packaging
LNBH24
www.st.com
1/30
30

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LNBH24 Summary of contents

Page 1

... LNB short circuit dynamic protection ■ +/- 4 kV ESD tolerant on output power pins Description Intended for analog and digital dual satellite receivers/sat-TV, sat-PC cards, the LNBH24 is a monolithic voltage regulator and interface IC, assembled in PowerSSO-36 ePad, specifically Table 1. Device summary Order code ...

Page 2

... Over-current and short-circuit protection and diagnostic . . . . . . . . . . . . . . 8 2.14 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 LNBH24 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/30 ...

Page 3

System register (SR, 1 Byte for each section A and 7.3 Transmitted data (I²C bus write mode) for each section A ...

Page 4

... B Control Control - - ² ² I²C Diagnostics I²C Diagnostics 22KHz 22KHz Oscill . Oscill . . . . . TEN- TEN TEN- TEN LNBH24 LNBH24 A-GND A-GND - - Byp Byp ISEL - B ISEL - TTX- B TTX Rsense Rsense EN- EN VSEL- VSEL- ...

Page 5

... R-L filter. 2.4 DiSEqC™ 1.X implementation When the LNBH24 is used in DiSEqC™ 1.x applications the R-L filter is always needed for the proper operation of the 22 kHz tone generator (patent pending. See this case, the TTX function must be preventively enabled before to start the 22 kHz data transmission and disabled as soon as the data transmission has been expired. The tone can ...

Page 6

... In order to improve design flexibility an external tone input pin is available (EXTM). The EXTM is a Logic input pin which activates the 22 kHz tone output, on the V the LNBH24 integrated tone generator (similar to the DSQIN pin function). In fact, the output tone waveform characteristics will always be internally controlled by the LNBH24 tone ...

Page 7

... In order for it to function even in a multi-IRD configuration (multi- switch), where the supply current could be sunk only from the higher supply voltage connected to the multi-switch box, the LNBH24 is provided with the AUX I²C bit. To force the LNBH24 output voltage as the highest voltage on the bus (22 V typ.) during the minimum current diagnostic phase, the AUX I² ...

Page 8

... Thermal protection and diagnostic The LNBH24 is also protected against overheating. When the junction temperature exceeds 150 °C (typ.), the step-up converter and the liner regulator are shut off, and the diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 135 ° ...

Page 9

... Serial data Bi-directional data from / to I²C BUS. Serial clock Clock from I²C BUS. These pins will accept the DiSEqC code from the main microcontroller. The LNBH24 will uses this code to modulate the internally-generated 22 kHz carrier. Set to ground if not used ...

Page 10

Table 2. Pin description (continued) Pin n° Symbol (sec. A/B) 18 TTX-A 2 TTX-B 17 DETIN-A Tone decoders 3 DETIN-B 15 DSQOUT- A DiSEqC outputs 5 DSQOUT EXTM-A 36 EXTM-B 10 P-GND-A Power grounds 9 P-GND-B ePad ePad ...

Page 11

Maximum ratings Table 3. Absolute maximum ratings Symbol power supply input voltage pins CC input voltage UP I Output current output pin voltage oRX V Tone output pin voltage ...

Page 12

Application circuit Figure 4. Typical application circuit C4a C4a C3a C3a C5b C5b C6b C6b L2a L2a 470nF 470nF 100µF 100µF 100µF 100µF 470nF 470nF Ferrite Ferrite Bead Bead D1a D1a STPS130A STPS130A L1a L1a 22µH 22µH Rsel-A Rsel-A ...

Page 13

Table 5. Bill of material (valid for A and B sections except for C1, C2, C7, C8 and R1) Component R1, R4 1/4 W resistors. Refer to the typical application circuit for the relative values R3, R 1/8 W resistors. ...

Page 14

... SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH24 will not generate acknowledge if the V supply is below the under-voltage lockout threshold (6.7 V typ.). ...

Page 15

Figure 5. Data validity on the I²C bus Figure 6. Timing diagram of I²C bus Figure 7. Acknowledge on the I²C bus 15/30 ...

Page 16

... LNBH24 software description The LNBH24 I²C interface controls both the IC sections A and B depending on the address sent before the DATA byte. The description below is valid for both sections. 7.1 Interface protocol The interface protocol comprises: ● A start condition (S) ● A chip address byte (the LSB bit determines read (=1)/write (=0) transmission) ● ...

Page 17

... I²C bus in read mode. The read mode is master activated by sending the chip address with R/W bit set the following master generated clock bits, the LNBH24 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: ● ...

Page 18

... Values are typical unless otherwise specified. 7.5 Power-on I²C interface reset The I²C interface built in the LNBH24 is automatically reset at power-ON. As long as the V stays below the undervoltage lockout (UVL) threshold (6.7 V), the interface will not respond to any I²C command and the system registers (SR) are initialized to all zeroes, thus keeping the power blocks disabled ...

Page 19

Electrical characteristics Refer to the typical application circuit in VSEL=LLC=TEN=PCL=ITEST=TTX=AUX= mA, unless otherwise stated. Typical values are referred to T voltage. See software description section for I²C access to the system register. Table 8. Electrical characteristics of ...

Page 20

Table 8. Electrical characteristics of sections A/B (continued) Symbol Parameter DC-DC converter switching F SW frequency Tone detector frequency F DETIN capture range V Tone detector input amplitude Sine wave signal, 22 kHz DETIN Tone detector input Z DETIN impedance ...

Page 21

T from ° Table 10. Address pins characteristics Symbol Parameter "0001000(R/W)" Address pin V ADDR-A1 voltage range for section A "0001001(RW)" Address pin V ADDR-A2 voltage range for section A "0001010(R/W)" Address pin V ADDR-B1 ...

Page 22

Refer to the typical application circuit in VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, R mA, unless otherwise stated. Typical values are referred to T description section for I²C access to the system register. Table 13. 22KHz tone diagnostic (TMON bit) characteristics of sections A/B Symbol ...

Page 23

Typical performance characteristics Refer to the typical application circuit in VSEL=LLC=TEN=PCL=ITEST=TTX=AUX= mA, unless otherwise stated. Typical values are referred to T Figure 8. Output voltage vs. temperature = ...

Page 24

Figure 14. Supply current vs. temperature =No Load =No Load CC CC OUT OUT Both Sections Enabled with ...

Page 25

Figure 20. Tone frequency vs. temperature OUT OUT EN=TEN=TTX=1 EN=TEN=TTX=1 ...

Page 26

Figure 26. DC-DC converter efficiency vs. temperature 100 100 750 mA = 750 OUT OUT 50 50 EN=VSEL=LLC=1 ...

Page 27

Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at ...

Page 28

PowerSSO-36 mechanical data Dim. Min. A 2. 0.18 c 0.23 D 10. 4.1 Y 4.9 ...

Page 29

Revision history Table 14. Document revision history Date Revision 11-Feb-2008 1 27-Aug-2008 2 07-Apr-2009 3 Changes Initial release. Modified mechanical data on page Modified Y dimension mechanical data 28. on page 28. 29/30 ...

Page 30

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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