DS2413 Maxim, DS2413 Datasheet - Page 3

• Manufacturer Part Number: DS2413
• Description: The DS2413 is a dual-channel programmable I/O 1-Wire® chip
• Manufacturer: Maxim

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Presence Detect Sample
Time (Notes 1, 20)
IO PIN, 1-Wire WRITE
Write-0 Low Time
(Notes 1, 17)
Write-1 Low Time
(Notes 1, 17)
IO PIN, 1-Wire READ
Read Low Time
(Notes 1, 18)
Read Sample Time
(Notes 1, 18)
PIO Pins
Leakage Current
Input Capacitance
Output low voltage
Input Low Voltage
Input High Voltage
(Note 21)
PARAMETER
System requirement.
Full R
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00 or DS2480B may be required. The DS2482-x00 may not
always detect the DS2413 presence pulse. For proper operation it may be necessary to disregard (force to 1) the PPD bit in the
DS2482-x00 status register.
The I-V characteristic is linear for voltages greater than 10V.
Capacitance on the data pin could be 800pF when V
after V
Guaranteed by design and simulation. Not production tested.
The voltage on IO needs to be less than or equal to V
V
V
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After V
The I-V characteristic is linear for voltages less than 1V.
Applies to a single DS2413 attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
t
pulse. t
Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of V
 in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V
duration for the master to pull the line low is t
 in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V
of the bus master. The actual maximum duration for the master to pull the line low is t
The I-V characteristic is linear for voltages greater than 7V.
t
t
Production tested for V
PDH
MSP
PDH
TL
TL
and V
maximum specifications are valid at V
is deemed to have ended when the voltage on IO drops below 80% of V
is a system required sample point and not directly production tested. Production testing is performed on related parameters
and t
PUP
PUP
TH
PDL
PUP
PDL
range guaranteed by design and simulation. not production tested. Production testing performed at a fixed R
is crossed during a rising edge on IO, the voltage on IO has to drop by at least V
TH
has been applied the parasite capacitance will not affect normal communications.
is deemed to have begun when the voltage on IO drops below 20% of V
. Parameter t
are functions of the internal supply voltage, which is a function of V
and the time at which the voltage is 20% of V
SYMBOL
IHP(min)
FPD
V
V
t
t
t
t
V
MSP
t
MSR
C
W0L
W1L
I
OLP
RL
LP
IHP
ILP
P
is guaranteed by design and simulation, not production tested.
. V
IHP(max)
Standard speed, V
Standard speed
Overdrive speed, V
Overdrive speed
Standard speed, V
Standard speed (Note 14)
Overdrive speed, V
(Note 14)
Overdrive speed (Note 14)
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Pin at 28V (Note 19)
(Note 5)
20mA load current
(Note 1)
(Note 1)
is guaranteed by design and simulation, not production tested.
PUPmax
W1Lmax
(5.25V). In any case, V
+ t
CONDITIONS
PUP
ILMAX
F
3 of 18
-  and t
is first applied. If a 2.2k resistor is used to pull up the data line, 2.5µs
REH
PUP
PUP
whenever the master drives the line low.
PUP
PUP
PUP
after V
.
> 4.5V
> 4.5V
W0Lmax
 4.5V
 4.5V
DS2413: 1-Wire Dual Channel Addressable Switch
TH
+ t
has been previously reached.
TL
F
< V
-  respectively.
PUP
TH
PUP
< V
on the leading edge of the presence-detect low
and the 1-Wire Recovery Times. The V
PUP
PUP
V
t
t
RLmax
RL
RL
.
0.3V
67.4
69.6
MIN
on the leading edge of the pulse.
PUP
7.7
9.1
8.5
60
62
1
7
8
5
5
1
+ 
+ 
HY
+ t
–
to be detected as logic '0'.
F
.
TYP
100
IL
IL
to V
to the input high threshold
TH
. The actual maximum
15 - 
MAX
2 - 
120
120
0.4
0.8
75
75
10
10
16
16
15
15
24
28
2
2
PUP
UNITS
value.
TH
µA
pF
µs
µs
µs
µs
µs
V
V
V
and