DS1388 Maxim, DS1388 Datasheet - Page 15

• Manufacturer Part Number: DS1388
• Description: The DS1388 I²C real-time clock (RTC), supervisor, and EEPROM is a multifunction device that provides a clock/calendar, programmable watchdog timer, power-supply monitor with reset, and 512 bytes of EEPROM
• Manufacturer: Maxim

Figure 6. I
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and the
STOP conditions is not limited, and is determined by
the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
(ACK) after the reception of each byte. The master
device must generate an extra clock pulse, which is
associated with this acknowledge bit. The DS1388
does not generate any acknowledge bits if access to
the EEPROM is attempted during an internal pro-
gramming cycle.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by generating a not-acknowledge (NACK) bit on
the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
SDA
SCL
IDLE
2
C Data Transfer Overview
CONDITION
START
I
2
ADDRESS
MSB FIRST
SLAVE
C RTC/Supervisor with Trickle Charger
1–7
R/W
8
____________________________________________________________________
ACK
9
MSB
1–7
REPEATED IF MORE BYTES
ARE TRANSFERRED
DATA
and 512 Bytes EEPROM
LSB
Figures 7 and 8 detail how data transfer is accom-
plished on the I
the R/W bit, two types of data transfer are possible:
8
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data are transferred with the
most significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a NACK is returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a repeat-
ed START condition. Since a repeated START
condition is also the beginning of the next serial
transfer, the bus is not released. Data are transferred
with the most significant bit (MSB) first.
ACK
9
2
MSB
C bus. Depending upon the state of
1–7
DATA
LSB
8
NACK
ACK/
9
STOP CONDITION
REPEATED START
15