MAXQ1740 Maxim, MAXQ1740 Datasheet - Page 2

• Manufacturer Part Number: MAXQ1740
• Description: The MAXQ1740 is a low-power microcontroller that integrates a triple-track magnetic stripe reader interface, an I²C interface, two SPI™ interfaces, and one universal synchronous/asynchronous receiver-transmitter (USART) interface
• Manufacturer: Maxim

The MAXQ1740 is a MAXQ20C-based microcontroller
intended for integration into magnetic card readers. It
can be interfaced directly to a 3-track magnetic card
reader head, allowing security features to be added to a
POS or ATM card reader right at the machine/card inter-
face. Encryption is provided by a hardware AES engine.
Security features include a self-destruct input for tamper
detection, code scrambling, and fast-wiping of the NV
SRAM in the event of a tamper detection and supply-
rail monitoring for overvoltage conditions. A 16KB flash
memory provides nonvolatile storage for user programs
and other static, nonvolatile data.
The device provides 1KB of fast-wipe NV SRAM and 128
bytes of data NV SRAM, which instantaneously zeroizes
its contents when a tamper is detected. The 128 byytes
can be used as data RAM or working RAM for the AES.
The fast-wipe feature ensures that any data in the 1KB of
memory is destroyed before any application software can
access it. Communication peripherals include a hard-
ware I
A 1-Wire port is available for system programming and
application debugging.
2
ENCRYPTION
GENERATOR
DESTRUCT
RANDOM-
C, a hardware USART, and two hardware SPIs.
WAKE-UP
NUMBER
ENGINE
USART
TIMER
INPUT
Magnetic Card Reader Security Microcontroller
SELF-
AES
MAXQ1740
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OSCILLATOR
INTERNAL
16KB FLASH MEMORY
6MHz
DATA/AES NV SRAM
1024B FAST-ERASE
WATCHDOG TIMER
6KB UTILITY ROM
256B FAST-WIPE
DATA NV SRAM
Detailed Description
MAXQ RISC
CPU
GND +1.7V TO +3.6V
ABRIDGED DATA SHEET
REGULATOR
MONITOR/
VOLTAGE
Block Diagram
16-BIT TIMER
16-BIT TIMER
MAG STRIPE
INTERFACE
INTERFACE
UP TO 16
3-TRACK
1-Wire
GPIO
I
SPI
SPI
2
C
The MAXQ20C core supports the Harvard memory archi-
tecture with separate 16-bit program and data address
buses. A fixed 16-bit instruction word is standard, but
data can be arranged in 8 or 16 bits. The MAXQ core is
implemented as a pipelined processor with performance
approaching 1MIPS per MHz. The 16-bit data path is
implemented around register modules, and each register
module contributes specific functions to the core. The
accumulator module consists of sixteen 16-bit registers
and is tightly coupled with the arithmetic logic unit (ALU).
Program flow is supported by a configurable soft stack.
Execution of instructions is triggered by data transfer
between functional register modules, or between a func-
tional register module and memory. Since data move-
ment involves only source and destination modules,
circuit switching activities are limited to active modules
only. For power-conscious applications, this approach
localizes power dissipation and minimizes switching
noise. The modular architecture also provides a maxi-
mum of flexibility and reusability that are important for a
microprocessor used in embedded applications.
The MAXQ instruction set is highly orthogonal. All arith-
metic and logical operations can use any register in
conjunction with the accumulator. Data movement is sup-
ported from any register to any other register. Memory
is accessed through specific data pointer registers with
auto increment/decrement support.
The microcontroller incorporates several memory types:
• 16KB flash memory
• 1152 bytes fast-wipe NV SRAM
• 128 bytes of instantaneous zeroization NV SRAM
• 6KB utility ROM
• RAM-based software stack
The NV SRAM is cleared by a DRS event. The 128-byte
memory can be used as general-purpose memory if
the AES function is not in use. Starting the AES engine
invalidates data stored in this memory. See Figure 5 for
the memory map.
MAXQ1740
Microprocessor
Memory