MAXQ612 Maxim, MAXQ612 Datasheet - Page 23

• Manufacturer Part Number: MAXQ612
• Description: The MAXQ612/MAXQ622 are low-power, 16-bit MAXQ® microcontrollers designed for low-power applications including universal remote controls, consumer electronics, and white goods
• Manufacturer: Maxim

Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
ROM consists of subroutines that can be called from
application software. These include the following:
• In-system programming (bootstrap loader) using
• In-circuit debug routines
• Test routines (internal memory tests, memory loader,
• User-callable routines for in-application flash memory
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of system code, or to one of the special rou-
tines mentioned. Routines within the utility ROM are user
accessible and can be called as subroutines by the
application software. More information on the utility ROM
functions is contained in the MAXQ622 User’s Guide.
Some applications require protection against unau-
thorized viewing of program code memory. For these
applications, access to in-system programming, in-
application programming, or in-circuit debugging func-
tions is prohibited until a password has been supplied.
The password is defined as the 16 words of physical
program memory at addresses 0010h to 001Fh.
Three password locks protect three different program
memory segments. When the PWL is set to one (power-
on reset default) and the contents of the memory at
addresses 0010h to 001Fh are any value other than FFh
or 00h, the password is required to access the utility
ROM, including in-circuit debug and in-system program-
ming routines that allow reading or writing of internal
memory. When PWL is cleared to zero, these utilities are
fully accessible without password. The PWLS bit uses a
password that is at ULDR + 0010 to ULDR + 001F, and
the PWLL uses a password at UAPP + 0010 to UAPP +
001F. The password is automatically set to all ones fol-
lowing a mass erase.
JTAG interface
etc.)
programming and fast table lookup
WD[1:0]
00
01
10
11
______________________________________________________________________________________
WATCHDOG CLOCK
Sysclk/2
Sysclk/2
Sysclk/2
Sysclk/2
15
18
21
24
Infrared Module and Optional USB
WATCHDOG INTERRUPT TIMEOUT
16-Bit Microcontrollers with
174.7ms
21.9ms
2.7ms
1.4s
The internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the applica-
tion software. If software is operating correctly, the coun-
ter is periodically reset and never reaches its maximum
count. However, if software operation is interrupted,
the timer does not reset, triggering a system reset and
optionally a watchdog timer interrupt. This protects the
system against electrical noise or electrostatic discharge
(ESD) upsets that could cause uncontrolled processor
operation. The internal watchdog timer is an upgrade to
older designs with external watchdog devices, reducing
system cost and simultaneously increasing reliability.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period can be programmed in a range of
2
ated when the timeout period expires if the interrupt
is enabled. All watchdog timer resets follow the pro-
grammed interrupt timeouts by 512 system clock cycles.
If the watchdog timer is not restarted for another full
interval in this time period, a system reset occurs when
the reset timeout expires.
The dedicated IR timer/counter module simplifies low-
speed infrared (IR) communication. The IR timer imple-
ments two pins (IRTX and IRRX) for supporting IR
transmit and receive, respectively. The IRTX pin has no
corresponding port pin designation, so the standard
PD, PO, and PI port control status bits are not present.
However, the IRTX pin output can be manipulated high
or low using the PWCN.IRTXOUT and PWCN.IRTXOE
bits when the IR timer is not enabled (i.e., IREN = 0).
15
to 2
24
system clock cycles. An interrupt is gener-
and Modulation Timer
IR Carrier Generation
WATCHDOG INTERRUPT (µs)
WATCHDOG RESET AFTER
Watchdog Timer
42.7
42.7
42.7
42.7
23