71M6531D Maxim, 71M6531D Datasheet - Page 48

• Manufacturer Part Number: 71M6531D
• Description: The 71M6531D/F and 71M6532D/F are highly integrated SoC devices with an MPU core, RTC, flash, and LCD driver
• Manufacturer: Maxim

are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should
then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to
a low-Z state.
Data Sheet 71M6531D/F-71M6532D/F
The timing diagrams in
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in
48
Control
3:0
Bit
7
6
5
4
SDATA output Z
SDATA (output)
SDATA output Z
SDATA (output)
EECTRL Byte Written
SCLK (output)
EECTRL Byte Written
SCLK (output)
Write -- With HiZ
CNT[3:0]
Write -- No HiZ
Name
BUSY
BUSY (bit)
WFR
BUSY (bit)
HiZ
RD
Read/
Write
Figure 11
W
W
W
W
Figure 11: 3-Wire Interface. Write Command, HiZ=0
Figure 12: 3-Wire Interface. Write Command, HiZ=1
© 2005-2010 TERIDIAN Semiconductor Corporation
R
Table 48: EECTRL Bits for the 3-Wire Interface
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during
the last byte of a Write command to cause the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ = 0.
Asserted while the serial data bus is busy. When the BUSY bit falls, an
INT5 interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immediately
after the last SCK rising edge.
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be sent
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA will simply obey the HiZ bit.
through
D7
D7
Figure 15
D6
D6
CNT Cycles (6 shown)
CNT Cycles (6 shown)
(LoZ)
D5
(LoZ)
D5
describe the 3-wire EEPROM interface behavior. All
D4
D4
Description
D3
D3
D2
D2
Figure 11
INT5
INT5
(HiZ)
FDS 6531/6532 005
through
Figure 15
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