MAX7360 Maxim, MAX7360 Datasheet - Page 14

• Manufacturer Part Number: MAX7360
• Description: The MAX7360 I²C-interfaced peripheral provides microprocessors with management of up to 64 key switches, with an additional eight LED drivers/GPIOs that feature constant-current, PWM intensity control, and rotary switch control options
• Manufacturer: Maxim

I
Driver/GPIOs with Integrated ESD Protection
is required on SDA. The MAX7360’s SCL line operates
only as an input. A pullup resistor is required on SCL if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Each transmission consists of a START (S) condition
(Figure 3) sent by a master, followed by the MAX7360
7-bit slave address plus R/W bit, a register address byte,
one or more data bytes, and finally, a STOP (P) condition.
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
One data bit is transferred during each clock pulse
(Figure 4). The data on SDA must remain stable while
SCL is high.
Figure 3. START and STOP Conditions
Figure 4. Bit Transfer
14
2
C-Interfaced Key-Switch Controller and LED
_____________________________________________________________________________________
SDA
SCL
SDA
SCL
CONDITION
START
S
START and STOP Conditions
DATA LINE STABLE;
DATA VALID
Bit Transfer
CHANGE OF DATA
ALLOWED
The acknowledge bit is a clocked 9th bit (Figure 5), which
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires
9 bits. The master generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse; therefore, the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the MAX7360, the MAX7360 generates
the acknowledge bit because the MAX7360 is the recipi-
ent. When the MAX7360 is transmitting to the master,
the master generates the acknowledge bit because the
master is the recipient.
Table 3. 2-Wire Interface Address Map
PIN AD0
GND
SDA
V
SCL
CC
DEVICE ADDRESS
A7
0
0
0
0
A6
1
1
1
1
A5
1
1
1
1
A4
1
1
1
1
A3
0
0
1
1
CONDITION
Acknowledge
A2
STOP
0
1
0
1
P
A1
0
0
0
0
R/W
R/W
R/W
R/W
A0