ISL45041IRZ Intersil, ISL45041IRZ Datasheet - Page 5

• Manufacturer Part Number: ISL45041IRZ
• Description: IC CALIBRATOR LCD MODULE 8-DFN
• Manufacturer: Intersil
• Type: Calibratorr

Specifications of ISL45041IRZ

• Applications: LCD Display
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application Information
This device provides the ability to reduce the flicker of an LCD
panel by adjustment of the V
test and alignment. A 128-step resolution is provided under
digital control, which adjusts the sink current of the output.
The output is connected to an external voltage divider, so that
the device will have the capability to reduce the voltage on the
output by increasing the output sink current.
The adjustment of the output is provided by the 2-wire I
serial interface.
Expected Output Voltage
The ISL45041 provides an output sink current, which lowers
the voltage on the external voltage divider (V
voltage). Equation 1 and Equation 2 can be used to calculate
the output current (I
The setting is the register value +1 with a value between 1
and 128.
I
V
Table 1 gives the calculated value of V
values of: R
AV
OUT
OUT
DD
FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE
SETTING VALUE
=
=
= 10V.
AVDD
Setting
-------------------- - x
⎛
⎜
⎝
-------------------- -
R
128
SET
ISL45041
1
SET
100
128
110
R
10
20
30
40
50
60
70
80
90
+
1
2
R
R
SET
2
= 24.9kΩ, R
-------------------------- -
20 R
⎞
⎟
⎠
AV
AV
OUT
(
OUT)
DD
DD
SET
I
OUT
⎛
⎜
⎝
1
)
TABLE 1.
and output voltage (V
–
AVDD
Setting
-------------------- - x
COM
1
128
= 200kΩ, R
5
R
R
1
2
voltage during production
-------------------------- -
20 R
OUT
(
-
+
R
V
5.486
5.313
5.141
4.969
4.797
4.625
4.453
4.281
4.109
3.936
3.764
3.592
3.282
SET
1
2
using the resistor
OUT
= 243kΩ, and
COM
)
⎞
⎟
⎠
OUT
output
) values.
(EQ. 1)
(EQ. 2)
2
C
ISL45041
R
The external R
maximum, that determines the lowest voltage of the external
voltage divider R
between the OUT pin and SET pin (Figure 2), which are also
the drain and source of the output transistor, must be greater
than 1.75V. This will keep the output transistor in its saturation
region to maintain linear operation over the full range of register
values. Expected current settings and 7-bit accuracy occurs
when the output MOS transistor is operating in the saturation
region. Figure 2 shows the internal connection for the output
MOS transistor. The value of the AV
at the source of the output transistor. This voltage is equal to
(Setting/128) x (AV
to (Setting/128) x (AV
calculated using Equation 2. The values of R
(Equation 2) should be determined using I
(setting equal to 128) so the minimum value of V
than 1.75V + AV
Ramp-Up of the VDD Power Supply
The ramp-up from 10% V
achieved in 10ms or less to ensure that the EEPROM and
power-on-reset circuits are synchronized and the correct
value is read from the EEPROM Memory.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 3. When applying power, VDD should be applied
before or at the same time as AVDD. The minimum time for
t
AVDD is not important.
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
VS
SET
A
AVDD
V
is 0µs. When removing power, the sequence of VDD and
FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE
VDD
DD
Resistor
FIGURE 3. POWER SUPPLY SEQUENCE
SETTING
----------------------------x
SET
128
DD
1
and R
DD
resistor sets the full-scale sink current, I
/20.
DD
/20). The I
AV
----------------- -
/20 x R
2
20
DD
(Figure 1). The voltage difference
DD
to 90% V
SET
t
SET
VS
). The drain voltage is
DD
OUT PIN
current is therefore equal
supply sets the voltage
DD
R
VSAT
0.5V
SET
OUT
level must be
1
and R
maximum
OUT
AV
December 17, 2010
DD
SET PIN
2
R1
R2
is greater
= 15V
FN6189.4
SET