LMH1983SQX/NOPB National Semiconductor, LMH1983SQX/NOPB Datasheet - Page 19

• Manufacturer Part Number: LMH1983SQX/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQX/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADD
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
Name
PLL1 Advanced
Control
N Counter MSB
PLL1 Advanced
Control
N Counter LSB
PLL1 Advanced
Control
Lock Step Size
PLL2 Advanced
Control
Main
PLL2 Advanced
Control
Charge Pump Current
PLL2 Advanced
Control
VCO Range
PLL3 Advanced
Control
Main
PLL3 Advanced
Control
Charge Pump Current
PLL3 Advanced
Control
VCO Range
PLL4 Advanced
Control
Main
PLL4 Advanced
Control
Charge Pump Current
PLL4 Advanced
Control
R counter
Bits
7
6:0
7:0
7:5
4:0
7:5
4
3
2:0
7:4
3:0
7:0
7:5
4
3
2:0
7:4
3:0
7:0
7:4
3
2
1
0
7:4
3:0
7
6:0
Field
RSVD
MSB
LSB
RSVD
Lock Step Size
RSVD
PLL2_DIV
PLL2_DISABLE
RSVD
RSVD
ICP2
VCO_RNG2
RSVD
PLL3_DIV
ICP3
RSVD
RSVD
ICP3
VCO_RNG3
PLL4_DIV
PLL4_Disable
RSVD
IS125M
PLL4_Mode
RSVD
ICP4
RSVD
DIV_R4
19
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0000110 The 7 LSBs of Register 0x2B along with the
0xB4
01000
0
0
0010
0x0C
0
0
0011
0x05
0010
0
0
0
1000
1001011 Sets the R divider in PLL4
Description
Reserved
eight bits of register 0x2C comprise the
fifteen bit word which is used for the N divider
of PLL1. These registers are internally
controlled based on the input format detected
and when AutoFormatDetect is enabled,
these registers are read only.
Reserved
See Applications section discussion on Lock
Detect
Reserved
0 = divide by 1
1 = divide by 2
0 = PLL2 disable is determined by
XPT_MODE (Address 0x09)
1 = PLL2 is disabled
Reserved
Reserved
Controls PLL2 Charge Pump Current
Controls the VCO range
Reserved
0 = divide by 1
1 = divide by 2
0 = PLL3 disable is determined by
XPT_MODE (Address 0x09)
1 = PLL3 is disabled
Reserved
Reserved
Controls PLL3 Charge Pump Current
Controls the VCO range
Controls the PLL4 output divider — PLL4 is
divided by 2
0 = PLL4 is enabled
1 = PLL4 is disabled
Reserved
0 = 100 MHz clock
1 = 125 MHz clock
0 = using 27 MHz Clock
1 = using external clock
Reserved
Controls PLL4 Charge Pump Current
Reserved
PLL4_DIV
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