TUA 6037F Infineon Technologies, TUA 6037F Datasheet - Page 26

• Manufacturer Part Number: TUA 6037F
• Description: IC TUNER MOPLL STAT 48-VQFN
• Manufacturer: Infineon Technologies
• Series: OMNITUNE™r
• Type: Tunerr

Specifications of TUA 6037F

• Package / Case: 48-VQFN
• Applications: NTSC, PAL
• Mounting Type: Surface Mount
• Bus Type: I2C
• Maximum Frequency: 863.25 MHz
• Minimum Frequency: 48.25 MHz
• Modulation Technique: FM
• Mounting Style: SMD/SMT
• Function: PAL, NTSC
• Noise Figure: 9 dB
• Operating Supply Voltage: 5 V
• Supply Voltage (min): 4.5 V
• Supply Voltage (max): 5.5 V
• Minimum Operating Temperature: - 40 C
• Maximum Operating Temperature: + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000315896

3.4.5
Data is exchanged between the processor and the PLL via the I
generated by the processor (input SCL). Pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have a hysteresis and a low-pass characteristic, which enhance the noise
immunity of the I
The data from the processor pass through an I
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are high). Each telegram begins with the start condition
and ends with the stop condition. Start condition: SDA goes low, while SCL remains high.
Stop condition: SDA goes high while SCL remains high. All further information transfer
takes place during SCL = low, and the data is forwarded to the control logic on the
positive clock edge.
The table ’Bit Allocation’ (see
All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which
the control logic returns the SDA line to low (acknowledge condition). The first byte is
comprised of seven address bits. These are used by the processor to select the PLL from
several peripheral components (address select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or
third data byte determines whether a divider ratio or control information is to follow. In
each case the second byte of the same data type has to follow the first byte. Appropriate
setting of the test bits will decide whether the band-switch byte or the auxiliary byte will
be transmitted (see
If the address byte indicates a READ operation, the PLL generates an acknowledge and
then shifts out the status byte onto the SDA line. If the processor generates an
acknowledge, a further status byte is output; otherwise the data line is released to allow
the processor to generate a stop condition. The status word consists of three bits from
the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by an appropriate DC level at pin AS (see
Table
While the supply voltage is applied, a power-on reset circuit prevents the PLL from
setting the SDA line to low, which would block the bus. The power-on reset flag POR is
set at power-on and if V
3.4.6
For the tuner prestage alignment a programmable switch is integrated to bypass the
bandpass, the SAW filter driver and the SAW filter. If "Loop thru" is active the mixer
output signal in front of the external bandpass is fed into the IF AGC amplifier as shown
in
Data Sheet
Figure
10).
5.
I
Loop thru
2
C-Bus Interface
2
C bus.
Table
CC
falls below 2 V. It will be reset at the end of a READ operation.
11).
Table
8) should be referred to for the following description.
26
2
C bus controller. Depending on their
TUA 6039F-2, TUA 6037F
Functional Description
Revision 2.0, 2007-07-20
2
C bus. The clock is