MAX4688 Maxim, MAX4688 Datasheet - Page 6

• Manufacturer Part Number: MAX4688
• Description: The MAX4686/MAX4687/MAX4688 low on-resistance (RON), low-voltage analog switches operate from a single +1
• Manufacturer: Maxim

Proper power-supply sequencing is recommended for all
CMOS devices. Always apply V+ before applying analog
signals, especially if the analog signal is not current limit-
ed. If this sequencing is not possible, and if the analog
inputs are not current limited to <20mA, add a small-sig-
nal diode (D1) as shown in Figure 1. Adding a protection
diode reduces the analog range to a diode drop (about
0.7V) below V+ (for D1). R
supply voltages. Maximum supply voltage (V+) must not
exceed +6V.Protection diode D1 also protects against
some overvoltage situations. No damage will result on
Figure 1’s circuit if the supply voltage is below the
absolute maximum rating and if a fault voltage up to the
absolute maximum rating is applied to an analog signal
pin.
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Ultra-Chip-Board-Scale Package).
2.5Ω, Low-Voltage, SPST/SPDT
Analog Switches in UCSP Package
Figure 2. Switching Time
Figure 3. Break-Before-Make Interval (MAX4688 only)
6
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MAX4686
MAX4687
MAX4688
MAX4688
LOGIC
INPUT
LOGIC
INPUT
V
N_
V
IN_
UCSP Package Consideration
C
V
OUT
C
L
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
OR NC
NC_
NO_
IN_
IN_
INCLUDES FIXTURE AND STRAY CAPACITANCE.
= V
GND
N_
ON
(
R
L
GND
R
+ R
L
increases slightly at low
ON
)
V+
V+
V+
V+
COM_
COM_
R
50Ω
R
300Ω
L
L
V
OUT
C
35pF
C
35pF
L
V
L
OUT
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. CSP reliability is integrally linked to the user’s
assembly methods, circuit board material, and usage
environment. The user should closely review these areas
when considering use of a CSP package. Performance
through Operating Life Test and Moisture Resistance
remains uncompromised as it is primarily determined by
the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a CSP package. CSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be considered.
Information on Maxim’s qualification plan, test data, and
recommendations are detailed in the UCSP application
note, which can be found on Maxim’s website at
www.maxim-ic.com.
OUTPUT
SWITCH
LOGIC
INPUT
LOGIC
INPUT
V
OUT
Test Circuits/Timing Diagrams
V+
0
0
V+
0
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V
t
50%
OUT
ON
50%
0.9 x V
t
D
0UT
UCSP Reliability
t
OFF
t r < 5ns
t f < 5ns
0.9 x V
0.9 x V
OUT
OUT
tr < 5ns
t
f
< 5ns