74LVC1G125GM,115 NXP Semiconductors, 74LVC1G125GM,115 Datasheet - Page 7

IC BUFF DVR TRI-ST N-INV 6XSON

74LVC1G125GM,115

Manufacturer Part Number
74LVC1G125GM,115
Description
IC BUFF DVR TRI-ST N-INV 6XSON
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC1G125GM,115

Package / Case
6-XSON (Micropak™), SOT-886
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
74LVC
Number Of Channels Per Chip
1
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
200 uA
Low Level Output Current
32 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
2.1 ns
Number Of Lines (input / Output)
1 / 1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4396-2
74LVC1G125GM-G
74LVC1G125GM-G
935277203115

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVC1G125GM,115
Manufacturer:
NXP Semiconductors
Quantity:
4 000
NXP Semiconductors
11. Dynamic characteristics
Table 8.
Voltages are referenced to GND (ground = 0 V). For test circuit see
[1]
[2]
[3]
[4]
[5]
74LVC1G125
Product data sheet
Symbol Parameter
t
t
t
C
pd
en
dis
PD
Typical values are measured at T
t
t
t
C
P
f
f
C
V
N = number of inputs switching;
(C
pd
en
dis
i
o
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
 V
propagation delay A to Y; see
enable time
disable time
power dissipation
capacitance
PD
Dynamic characteristics
CC
 V
2
 f
CC
o
2
) = sum of outputs.
 f
PLH
PZH
PLZ
i
 N + (C
and t
and t
and t
PHL
PZL
PHZ
Conditions
OE to Y; see
OE to Y; see
per buffer; V
L
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
output enabled
output disabled
 V
amb
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
= 25 C and V
2
 f
Figure 7
o
All information provided in this document is subject to legal disclaimers.
I
) where:
Figure 8
Figure 8
= GND to V
Rev. 9 — 29 December 2010
CC
= 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
CC
D
in W).
[2]
[3]
[4]
[5]
Figure
Min
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
-
-
40 C to +85 C
9.
Typ
3.3
2.2
2.5
2.1
1.7
4.1
2.8
3.3
2.4
2.1
4.3
2.7
3.0
3.1
2.2
25
6
[1]
Max
8.0
5.5
5.5
4.5
4.0
9.4
6.6
6.6
5.3
5.0
9.2
5.0
5.0
5.0
4.2
-
-
Bus buffer/line driver; 3-state
74LVC1G125
40 C to +125 C Unit
Min
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
-
-
© NXP B.V. 2010. All rights reserved.
Max
10.5
5.5
8.5
8.5
6.5
6.5
6.5
6.5
5.5
12
12
7
7
6
7
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
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