TLE84106EL Infineon Technologies, TLE84106EL Datasheet - Page 21

• Manufacturer Part Number: TLE84106EL
• Manufacturer: Infineon Technologies

Specifications of TLE84106EL

• Packages: PG-SSOP-24
• Ipeak: 6 x 0.8
• Inhibit: y
• Iq (typ): 2.0 µA
• Mounting: SMIT
• Technology: BCD

6
6.1
The SPI is used for bidirectional communication with a control unit. The TLE84106EL acts as SPI-slave and the
control unit acts as SPI-master. The 16-bit control word is read via the SDI serial data input. The status word
appears synchronously at the SDO serial data output. The communication is synchronized by the serial clock input
SCLK.
Standard data transfer timing is shown in
be low during CSN transition. The transfer is MSB first.
The transmission cycle begins when the chip is selected with the chip-select-not (CSN) input (H to L). Then the
data is clocked through the shift register. The transmission ends when the CSN input changes from L to H and the
word which has been read into the shift register becomes the control word. The SDO output switches then to
tristate status, thereby releasing the SDO bus circuit for other uses. The SPI allows to parallel multiple SPI devices
by using multiple CSN lines. The SPI can also be used with other SPI-devices in a daisy-chain configuration.
The control word transmitted from the master to the TLE84106EL is executed at the end of the SPI transmission
( CSN L -> H ) and remains valid until a different control word is transmitted or a power on reset occurs. At the
beginning of the SPI transmission ( CSN H -> L ), the diagnostic data currently valid are latched into the SPI and
transferred to the master.
Data integrity is maintained by polling multiples of 8 data bits to ensure that a valid command has been received.
Figure 11
Data Sheet
SPI
General
SPI Data Transfer Protocol
Figure
11. The clock polarity is data valid on falling edge. SCLK must
21
Hex Half Bridge IC
Rev. 1.0, 2010-04-27
TLE84106EL
SPI