AD9953 Analog Devices, AD9953 Datasheet
AD9953
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AD9953 Summary of contents
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... SYNC 4 Control Registers M U System Clock X 4x-20x Clock Multipler PS<1:0> IO Port One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 AD9953 14 19 DAC COS(x) System Clock θ Reset www.analog.com © 2003 Analog Devices, Inc. All rights reserved. DAC I-set ...
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... Amplitude Ramp Rate (ARR) Frequency Tuning Word 0 (FTW0) Phase Offset Word (POW) REV. PrB 3/4/03 tuning word). The frequency tuning and control words are loaded into the AD9953 via a serial I/O port. The AD9953 includes an integrated 1024x32 Static RAM to support flexible frequency to form a digitally- sweep capability in several modes ...
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... Synchronization; Register Updates (I/O UPDATE) Functionality of the SyncClk and I/O UPDATE Figure D- I/O Synchronization Block Diagram Figure E - I/O Synchronization Timing Diagram Synchronizing Multiple AD9953s Using a Single Crystal To Drive Multiple AD9953 Clock Inputs Serial Port Operation Instruction Byte Serial Interface Port Pin Description MSB/LSB Transqfers Example Operation ...
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... PRELIMINARY TECHNICAL DATA AD9953 PRELIMINARY ELECTRICAL SPECIFICATIONS =+1.8 V ±5%, R (Unless otherwise noted Multiplier enabled at 20×) Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4X REFCLK Multiplier Enabled at 20X Input Capacitance Input Impedance Duty Cycle Duty Cycle with REFCLK Multiplier Enabled ...
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... 1.25 I 0.6 I 2 1. TBD I TBD I TBD I TBD I TBD Analog Devices, Inc. AD9953 Units dBc dBc MHz SYSCLK cycles µA µ ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9953 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Figure 1 AD9953 Pinmap Page RESET PwrDwnCtl 34 DVDD 33 DGND AGND 32 AGND 31 30 AGND AVDD 29 ...
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... A resistor (3.85KΩ nominal) connected from AGND to DAC_Rset establishes the reference current for the DAC connect. I Input pin used as an external power down control. See the External Power Down Control section of this document for details. Page 8 AD9953 Analog Devices, Inc. ...
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... PS0, PS1 REV. PrB 3/4/03 I Active high hardware reset pin. Assertion of the RESET pin forces the AD9953 to the initial state, as described in the IO Port Register map. I Asynchronous active high reset of the serial port controller. When high, the current IO operation is immediately terminated enabling a new IO operation ...
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... The AD9953 frequency tuning word(s) are unsigned numbers, where 80000000(hex) represents the highest output frequency possible, commonly referred to as the Nyquist frequency. Values ranging from than 80000001(hex) to FFFFFFFF (hex) will be expressed as aliased frequencies less than Nyquist. An example using a 3-bit phase accumulator will illustrate this principle. For a tuning word of 001, the phase accumulator output (PAO) increments from all zeros to all ones and repeats when the accumulator overflows after clock cycle number 8 ...
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... The AD9953 supports various clock methodologies. Support for differential or single-ended input clocks, enabling of an on-chip oscillator and/or phase-locked loop (PLL) multiplier are all controlled via user programmable bits. The AD9953 may be configured in one of six operating modes to generate the system clock. The modes are configured using the ClkModeSelect pin, CFR1< ...
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... The PLL is bypassed by programming a value outside the range of 4-20 (decimal). When bypassed, the PLL is shut down to conserve power. DAC Output The AD9953 incorporates an integrated 14-bit current output DAC. Two complementary outputs provide a combined full-scale output current (I common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-to-noise ratio ...
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... Motorola 6905/11 SPI and Intel 8051 SSR protocols. The interface allows read/write access to all registers that configure the AD9953. MSB first or LSB first transfer formats are supported. In addition, the AD9953’s serial interface port can be configured as a single pin I/O (SDIO), which allows a two-wire interface or two unidirectional pins for in/out (SDIO/SDO), which enables a three wire interface ...
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... Frequency <7:0> Tuning <15:8> Word <23:16> (FTW0) <31:24> (04h) Phase <7:0> Offset Word <15:8> Not used<1:0> (POW0) (05h) REV. PrB 3/4/03 AD9953 Register Map Bit 6 Bit 5 Bit 4 Not Used DAC Clock Input Power Power Dwn Down AutoClr AutoClr Enable Freq. Phase SINE Accum Accum Output Software ...
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... Active RAM Segment 3 Beginning Address <5:0> RAM Segment 3 Final Address <7:0> RAM Segment 3 Address Ramp Rate <15:8> RAM Segment 3 Address Ramp Rate <7:0> RAM [1023:0] <31:0> (Read Instructions write out RAM Signature Register data) Page 15 AD9953 PS0=0 PS1=0 RAM Segment 0 PS0=0 Final Address <9:8> PS1=0 PS0=0 PS1=0 ...
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... When CFR1<26> (default), the amplitude ramp rate timer is loaded only upon timeout (timer ==1) and is NOT loaded due to an I/O UPDATE input signal. When CFR1<26> the amplitude ramp rate timer is loaded upon timeout (timer == the time of an I/O UPDATE input signal. REV. PrB 3/4/03 Page 16 AD9953 Analog Devices, Inc. ...
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... When CFR1<22> the software controlled manual synchronization of multiple AD9954s feature is executed. The SYNC_CLK rising edge is advanced by one SYSCLK cycle and this bit is cleared. To advance the rising edge multiple times, this bit needs to be set for each advance. See the Synchronizing Multiple AD9953s section of this document for details. . ...
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... When CFR1<16> phase dithering for truncated phase words, bit 13 of <31:13>, is enabled. CFR1<14>: Auto Clear Frequency Accumulator bit. When CFR1<14> (default), a new delta frequency word is applied to the input normal operation, but not loaded into the accumulator. REV. PrB 3/4/03 Page 18 AD9953 Analog Devices, Inc. ...
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... When CFR1<10> (default), the phase accumulator functions as normal. When CFR1<10> the phase accumulator memory elements are asynchronously cleared. CFR1<9>: SDIO Input Only. When CFR1<9> (default), the SDIO pin has bi-directional operation (2-wire serial programming mode). REV. PrB 3/4/03 Page 19 AD9953 Analog Devices, Inc. ...
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... When CFR1<3> the external power down mode selected is the “full power down” mode. In this mode, when the PwrDwnCtl input pin is high, all functions are powered down. This includes the DAC and PLL, which take a significant amount of time to power up. REV. PrB 3/4/03 Page 20 AD9953 Analog Devices, Inc. ...
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... Control Function Register #2 (CFR2) The CFR2 is comprised of three bytes located in parallel addresses 06h-04h. The CFR2 is used to control the various functions, features, and modes of the AD9953, primarily related to the analog sections of the chip. All bits of the CFR2 will be routed directly to the Analog section of the AD9953 as a single 24-bit bus labeled CFR2< ...
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... The ARR register stores the 8-bit Amplitude Ramp Rate used in the Auto OSK mode, that is CFR1<25>=1, CFR<24>=1. This register programs the rate the amplitude scale factor counter increments or decrements. In the OSK is set to manual mode, CFR1<25>=1 CFR<24>= OSK enable is cleared CFR1<25>=0, this register has no affect on device operation. REV. PrB 3/4/03 Page 22 AD9953 Analog Devices, Inc. ...
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... RAM modes of operation. RAM The AD9953 incorporates a 1024x32 block of SRAM. The RAM is bi-directional single- port. That is to say, both READ and WRITE operations from and to the RAM are valid, but they cannot occur simultaneously. WRITE operations from the serial I/O port have precedence, and if an attempt to WRITE to RAM is made during a READ operation, the READ operation will be halted ...
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... When CFR1<31> is logic zero, the RAM is inactive unless being written to via the serial port. The power up state of the AD9953 is single tone mode, in which the RAM Enable bit is inactive. The RAM is segmented into four unique slices controlled by the Profile< ...
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... The user must insure that the beginning address is lower than the final address. 2) Changing profiles automatically terminates the current sweep and starts the next sweep. 3) The AD9953 offers no output signal indicating when a terminal frequency has been reached. Setting the RAM destination bit true such that the RAM output drives the phase-offset adder 4) is valid ...
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... PRELIMINARY TECHNICAL DATA Bi-directional Ramp mode allows the AD9953 to offer a symmetrical sweep between two frequencies using the Profile<0> signal as the control input. The AD9953 is programmed for Bi- directional Ramp mode by writing the RAM Enable bit true and the RAM Mode Control bits of RSCW0 to logic 010(b). In Bi-directional Ramp mode, the Profile< ...
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... Continuous Re-circulate Mode Continuous Re-circulate mode allows the AD9953 to offer an automatic, continuous unidirectional sweep between two frequencies. The AD9953 is programmed for Continuous Re-circulate mode by writing the RAM Enable bit true and the RAM Mode Control bits of each profile to be used to logic 100(b). ...
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... Continuous Re-circulate 101,110,111 OPEN Internal Profile Control The AD9953 offers a mode in which a composite frequency sweep can be built, for which the timing control is software programmable. The “internal profile control” capability disengages the REV. PrB 3/4/03 Mode No sweeping, Profiles valid, No Dwell invalid ...
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... PRELIMINARY TECHNICAL DATA Profile<1:0> pins and enables the AD9953 to take control of switching between profiles. Modes are defined that allow continuous or single burst profile switches for three combinations of profile selection bits. These are listed in the table below. When the any of the CFR1<29:27> bits are active, the internal profile control mode is engaged ...
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... The third method of phase control involves the RAM and the profile input pins. The AD9953 can be configured such that the RAM drives the phase adjust circuitry. The user can control the phase offset via the RAM in an identical manner allowed for frequency sweeping ...
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... When high, amplitude dithering is enabled. Shaped On-Off Keying General Description: The Shaped On-Off keying function of the AD9953 allows the user to control the ramp-up and ramp-down time of an “on-off” emission from the DAC. This function is used in “burst transmissions” of digital data to reduce the adverse spectral impact of short, abrupt bursts of data ...
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... To DAC 1 OSK Enable CFR<25> OSK Pin Out inc/dec Enable Auto Scale Factor Generator Page 32 AUTO OSK Enable CFR<24> Load OSK Timer SyncClock CFR1<26> Amplitude Ramp Rate Register (ARR) HOLD Data Load Up/Dn EN Ramp Rate Timer Analog Devices, Inc. AD9953 Clock ...
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... CFR1<24> logic 0. When configured for external Shaped On-Off Keying, the content of the ASFR becomes the scale factor for the data path. The scale factors are synchronized to sync_clk via the I/O update functionality. REV. PrB 3/4/03 Increment/decrement size Page 33 AD9953 Analog Devices, Inc. ...
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... Synchronization; Register Updates (I/O UPDATE) Functionality of the SyncClk and I/O UPDATE Data into the AD9953 is synchronous to the sync_clk signal (supplied externally to the user on the SYNC_CLK pin). The I/O_UPDATE pin is sampled on the rising edge of the sync_clk. Internally, sysclk is fed to a divide-by-4 frequency divider to produce the sync_clk signal. ...
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... SYNCCLK Gating Register I/O Buffer Latches Memory Figure D- I/O Synchronization Block Diagram A B Data(2) Data(2) The device registers an I/O Update at point A. The data is tranferred from the asynchronously loaded I/O buffers at point B. Page 35 SyncClk Disable I/O UPDATE Profile<1:0> SCLK SDI CS Data(3) Data(3) Analog Devices, Inc. AD9953 ...
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... The AD9953 crystal oscillator output signal is available on the CrystalOut pin, enabling one crystal to drive multiple AD9953s. In order to drive multiple AD9953s with one crystal, the CrystalOut pin of the AD9953 using the external crystal should be connected to the REFCLK input of the other AD9953. REV. PrB 3/4/03 ...
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... At the completion of any communication cycle, the AD9953 serial port controller expects the next 8 rising SCLK edges to be the instruction byte of the next communication cycle.All data input to the AD9953 is registered on the rising edge of SCLK. All data is driven out of the AD9953 on the falling edge of SCLK. Figures are useful in understanding the general operation of the AD9953 Serial Port ...
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... PRELIMINARY TECHNICAL DATA Instruction Byte The instruction byte contains the following information as shown in the table below: Instruction Byte Information MSB REV. PrB 3/4/ Table 6 Instruction Byte Page 38 AD9953 D1 LSB A1 A0 Analog Devices, Inc. ...
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... Serial Interface Port Pin Description SCLK — Serial Clock. The serial clock pin is used to synchronize data to and from the AD9953 and to run the internal state machines. SCLK maximum frequency is 25 MHz. CSB — Chip Select Bar. Active low input that allows more than one device on the same serial communications line ...
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... PRELIMINARY TECHNICAL DATA operation is complete. All data written to (read from) the AD9953 must be (will be) in MSB first order. If the LSB mode is active, the serial port controller will generate the least significant byte address first followed by the next greater significant byte addresses until the IO operation is complete ...
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... PRELIMINARY TECHNICAL DATA Notes on Serial Port Operation 1) The AD9953 serial port configuration bits reside in bits 8 and 9 of CFR1 (address 00h). The configuration changes immediately upon writing to this register. For multi-byte transfers, writing to this register may occur during the middle of a communication cycle. Care must be taken to compensate for this new configuration for the remainder of the current communication cycle ...
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... PRELIMINARY TECHNICAL DATA When the CFR1<3> bit is zero, and the PwrDwnCtl input pin is high, the AD9953 is put into a “fast recovery power down” mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC bias circuitry, comparator, PLL, oscillator, and clock input circuitry is NOT powered down. The comparator can be powered down by setting the Comparator Power Down Bit, CFR1< ...