BLM21PG221SN1B Murata, BLM21PG221SN1B Datasheet
BLM21PG221SN1B
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March 2001, ver. 6.1 Features... f Table 1. MAX 7000 Device Features Feature EPM7032 Usable 600 gates Macrocells 32 Logic array 2 blocks Maximum 36 user I/O pins t (ns (ns (ns) 2.5 FSU ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 2. MAX 7000S Device Features Feature EPM7032S Usable gates 600 Macrocells 32 Logic array 2 blocks Maximum 36 user I/O pins t (ns (ns) 2 (ns) ...
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General Description Table 3. MAX 7000 Speed Grades Device - EPM7032 v v EPM7032S v EPM7064 v v EPM7064S EPM7096 EPM7128E v EPM7128S EPM7160E v EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S Altera Corporation MAX 7000 Programmable Logic Device Family ...
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MAX 7000 Programmable Logic Device Family Data Sheet 4 The MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E devices—have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew ...
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Table 5. MAX 7000 Maximum User I/O Pins Device 44- 44- Pin Pin PLCC PQFP EPM7032 36 36 EPM7032S 36 EPM7064 36 EPM7064S 36 EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S Notes: (1) When the JTAG interface in ...
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MAX 7000 Programmable Logic Device Family Data Sheet f Functional Description 6 MAX 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array ...
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Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram INPUT/GLCK1 INPUT/GCLRn INPUT/OE1 INPUT/OE2 I Control I/O pins Block I Control I/O pins Block Altera Corporation MAX 7000 Programmable ...
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MAX 7000 Programmable Logic Device Family Data Sheet Figure 2. MAX 7000E & MAX 7000S Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 Output Enables 6 to16 I I/O Pins Control Block 6 6 to16 6 to16 ...
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Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell Logic Array 36 Signals 16 Expander from PIA Product Ter Ter T ms Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals: 36 ...
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MAX 7000 Programmable Logic Device Family Data Sheet Figure 4. MAX 7000E & MAX 7000S Device Macrocell Logic Array 36 Signals 16 Expander from PIA Product Terms 10 Figure 4 shows a MAX 7000E and MAX 7000S device macrocell. Global ...
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Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes global clock signal. This mode achieves the fastest clock-to- output performance global clock signal and enabled ...
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MAX 7000 Programmable Logic Device Family Data Sheet 12 Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into ...
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Figure 6. Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. 36 Signals 16 Shared from PIA Expanders Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The compiler can allocate up to ...
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MAX 7000 Programmable Logic Device Family Data Sheet 14 Programmable Interconnect Array Logic is routed between LABs via the programmable interconnect array (PIA). This global bus is a programmable path that connects any signal source to any destination on the ...
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Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 8. I/O Control Block of MAX 7000 Devices EPM7032, EPM7064 & EPM7096 Devices OE1 OE2 From Macrocell To PIA MAX 7000E & MAX 7000S Devices PIA From Macrocell Fast ...
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MAX 7000 Programmable Logic Device Family Data Sheet In-System Programma- bility (ISP) 16 When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When ...
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Programmable Speed/Power Control Output Configuration Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet For more information on using the Jam language, see (Using the Jam Language for ISP & ICR via an Embedded The ISP circuitry in ...
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MAX 7000 Programmable Logic Device Family Data Sheet Programming with External Hardware Open-Drain Output Option (MAX 7000S Devices Only) MAX 7000S devices provide an optional open-drain (functionally equivalent to open-collector) output for each I/O pin. This open-drain ...
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IEEE Std. 1149.1 (JTAG) Boundary-Scan Support Table 6. MAX 7000 JTAG Instructions JTAG Instruction Devices SAMPLE/PRELOAD EPM7128S EPM7160S EPM7192S EPM7256S EXTEST EPM7128S EPM7160S EPM7192S EPM7256S BYPASS EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S IDCODE EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S ISP ...
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MAX 7000 Programmable Logic Device Family Data Sheet 20 The instruction register length of MAX 7000S devices is 10 bits. and 8 show the boundary-scan register length and device IDCODE information for MAX 7000S devices. Table 7. MAX 7000S Boundary-Scan ...
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Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 9 shows the timing requirements for the JTAG signals. Figure 9. MAX 7000 JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU ...
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MAX 7000 Programmable Logic Device Family Data Sheet f Design Security Generic Testing QFP Carrier & Development Socket f 22 For more information, see Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera All MAX 7000 devices contain a ...
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Operating Conditions Table 10. MAX 7000 5.0-V Device Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage output current, per pin OUT T Storage temperature STG T Ambient temperature AMB T Junction temperature ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 12. MAX 7000 5.0-V Device DC Operating Conditions Symbol Parameter V High-level input voltage IH V Low-level input voltage IL V 5.0-V high-level TTL output voltage I OH 3.3-V high-level TTL ...
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Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input voltage on I/O pins is –0.5 V and on 4 dedicated input pins is –0.3 V. During transitions, the inputs may undershoot to –2.0 ...
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MAX 7000 Programmable Logic Device Family Data Sheet Figure 12. MAX 7000 Timing Model Input Delay PIA Delay t PIA Notes: (1) Only available in MAX 7000E and MAX 7000S devices. (2) Not available in 44-pin devices. ...
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Figure 13. Switching Waveforms t & t < Inputs are driven for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Shared Expander Parallel ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 16. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered output PD2 t Global clock setup time SU t ...
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Table 17. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Fast input delay FIN t Shared expander delay SEXP t Parallel expander ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 18. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered output PD2 t Global clock setup time SU t ...
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Table 19. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Fast input delay FIN t Shared expander delay SEXP t Parallel expander ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 20. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered output PD2 t Global clock setup time SU t ...
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Table 21. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Fast input delay FIN t Shared expander delay SEXP t Parallel expander ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 22. MAX 7000 & MAX 7000E External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered PD2 output t Global clock setup time SU t ...
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Table 23. MAX 7000 & MAX 7000E Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Fast input delay FIN t Shared expander delay SEXP t Parallel expander ...
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MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) This parameter applies to MAX 7000E devices only. (2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t must ...
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Table 24. EPM7032S External Timing Parameters (Part Symbol Parameter f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Table 25. EPM7032S Internal Timing Parameters (Part Symbol Parameter t Input pad and ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 25. EPM7032S Internal Timing Parameters (Part Symbol Parameter t Register clear time CLR t PIA delay PIA t Low-power adder LPA Notes to tables: (1) This minimum pulse ...
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Table 26. EPM7064S External Timing Parameters (Part Symbol Parameter t Array clock to output delay ACO1 t Array clock high time ACH t Array clock low time ACL t Minimum pulse width for clear CPPW and preset ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 27. EPM7064S Internal Timing Parameters (Part Symbol Parameter t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD ...
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Table 28. EPM7128S External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered PD2 output t Global clock setup time SU t Global clock hold time H t Global clock setup time of fast ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 29. EPM7128S Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Fast input delay FIN t Shared expander delay ...
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Notes to tables: (1) This minimum pulse width for preset and clear applies for both global clear and array controls. The t must be added to this minimum width if the clear or reset signal incorporates the t path. (2) ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 30. EPM7160S External Timing Parameters (Part Symbol Parameter f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Table 31. EPM7160S Internal Timing Parameters (Part 1 ...
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Table 31. EPM7160S Internal Timing Parameters (Part Symbol Parameter t Register clear time CLR t PIA delay PIA t Low-power adder LPA Notes to tables: (1) This minimum pulse width for preset and clear applies for both ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 32. EPM7192S External Timing Parameters (Part Symbol Parameter t Array clock to output delay ACO1 t Array clock high time ACH t Array clock low time ACL t ...
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Table 33. EPM7192S Internal Timing Parameters (Part Symbol Parameter t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD t Combinatorial delay COMB t Array clock delay ...
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MAX 7000 Programmable Logic Device Family Data Sheet Table 34. EPM7256S External Timing Parameters Symbol Parameter t Input to non-registered output PD1 t I/O input to non-registered PD2 output t Global clock setup time SU t Global clock hold time ...
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Table 35. EPM7256S Internal Timing Parameters Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer delay IO t Fast input delay FIN t Shared expander delay SEXP t Parallel expander delay PEXP t Logic ...
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MAX 7000 Programmable Logic Device Family Data Sheet Notes to tables: (1) This minimum pulse width for preset and clear applies for both global clear and array controls. The t must be added to this minimum width if the clear ...
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Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 36. MAX 7000 I Equation Constants CC Device EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S This calculation provides an I using a pattern ...
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MAX 7000 Programmable Logic Device Family Data Sheet Figure 14. I vs. Frequency for MAX 7000 Devices (Part EPM7032 180 Room Temperature 140 Typical I CC 100 Active (mA) 60 60.2 ...
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Figure 14. I vs. Frequency for MAX 7000 Devices (Part EPM7128E 500 Room Temperature 400 Typical I 300 CC Active (mA) 200 55.5 MHz 100 Low Power 0 50 100 Frequency ...
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MAX 7000 Programmable Logic Device Family Data Sheet Figure 15. I vs. Frequency for MAX 7000S Devices (Part EPM7032S Room Temperature Typical I CC Active (mA) 30 58.8 ...
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Figure 15. I vs. Frequency for MAX 7000S Devices (Part EPM7192S Room Temperature Typical I CC Active (mA) 180 120 Device Pin-Outs Altera ...
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MAX 7000 Programmable Logic Device Family Data Sheet Figure 16. 44-Pin Package Pin-Out Diagram Package outlines not drawn to scale. Pin 1 (2) I/O/(TDI) I/O I/O GND I/O I/O EPM7032 (2) I/O/(TMS) I/O VCC I/O I/O Pin 12 44-Pin PQFP ...
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Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 17. 68-Pin Package Pin-Out Diagram Package outlines not drawn to scale. I/O 10 VCCIO 11 (2) I/O/(TDI) 12 I/O 13 I/O 14 I/O 15 GND 16 I/O 17 I/O ...
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MAX 7000 Programmable Logic Device Family Data Sheet Figure 18. 84-Pin Package Pin-Out Diagram Package outline not drawn to scale. (3) (3) Notes: (1) Pins 6, 39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM7160E, and EPM7160S devices. ...
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Figure 19. 100-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 EPM7064 EPM7096 EPM7128E EPM7128S EPM7160E Pin 31 100-Pin PQFP Figure 20. 160-Pin Package Pin-Out Diagram Package outline not drawn to scale ...
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MAX 7000 Programmable Logic Device Family Data Sheet Figure 21. 192-Pin Package Pin-Out Diagram Package outline not drawn to scale. Figure 22. 208-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin ...
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Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet 61 ...
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MAX 7000 Programmable Logic Device Family Data Sheet ® Altera, BitBlaster, ByteBlaster, JAM, MasterBlaster, MAX, MAX+PLUS II, MultiVolt, Quartus, Turbo Bit, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States 101 Innovation Drive ...