DS1996L-F5 Maxim Integrated Products, DS1996L-F5 Datasheet
DS1996L-F5
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DS1996L-F5 Summary of contents
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... Presence detector acknowledges when reader first applies voltage § Designed to meet UL#913 (4 Intrinsically Safe Apparatus, Under Entity Concept for use in Class I, Division 1, Group and D Locations, contact Dallas Semiconductor for certification schedule ORDERING INFORMATION DS1996L-F5 ® EXAMPLES OF ACCESSORIES DS9096P DS9101 DS9093RA DS9093F DS9092 ...
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DESCRIPTION The DS1996 Memory iButton is a rugged read/write data carrier that acts as a localized database that can be easily accessed with minimal hardware. The nonvolatile memory offers a simple solution to storing and retrieving vital information pertaining ...
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DS1996 BLOCK DIAGRAM Figure ...
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HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 BUS 1-WIRE BUS MASTER COMMAND LEVEL: 1-WIRE ROM FUNCTION COMMANDS (SEE FIGURE 9) DS 1996- SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 7) 64-BIT LASERED ROM Figure 3 8-Bit CRC Code MSB LSB MSB ...
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MEMORY The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages called memory. The DS1996 contains 256 pages which comprise the 65536-bit SRAM. The scratchpad is an additional page that acts as a ...
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Write Scratchpad Command [0FH] After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the ...
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MEMORY FUNCTION FLOW CHART Figure TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD=1 2) RESET PULSE TO BE TRANSMITTED AT OVERDRIVE SPEED IF OD=1; RESET PULSE TO BE TRANSMITTED AT REGULAR SPEED IF OD ...
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MEMORY FUNCTION EXAMPLES Example: Write two data bytes to memory locations 0026h and 0027h (the seventh and 8th bytes of page 1). Read entire memory. MASTER MODE DATA (LSB FIRST ...
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Copy Scratchpad [55H] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern which is obtained by reading the scratchpad for verification. This pattern ...
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Speed) or more than 120 µs (regular speed), one or more of the devices on the bus may be reset. HARDWARE CONFIGURATION Figure 8 TRANSACTION SEQUENCE The protocol for accessing the DS1996 via the ...
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Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1996 on a multidrop bus. Only the DS1996 that exactly matches the 64-bit ROM sequence will respond to the ...
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SIGNALING The DS1996 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data. All these signals ...
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ROM FUNCTIONS FLOW CHART Figure TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD=1 2) THE PRESENCE PULSE WILL BE SHORT IF OD ...
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ROM FUNCTIONS FLOW CHART Figure 9 (cont’d) 3) ALWAYS TO BE TRANSMITTED AT OVERDRIVE SPEED ...
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INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10 RESISTOR MASTER DS1996 * In order not to mask interrupt signaling by other devices on the 1-Wire bus, t less than 960 ms. READ/WRITE TIME SLOTS The definitions of write and read ...
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READ/WRITE TIMING DIAGRAM Figure 11 (cont’d) Write-Zero Time Slot Read-Data Time Slot RESISTOR MASTER DS1996 Regular Speed 60 ms £ t < 120 ms < t LOW0 SLOT 1 ms £ t < ¥ REC Regular Speed 60 ms £ ...
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PHYSICAL SPECIFICATIONS Size Weight Humidity Altitude Expected Service Life ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature * This is a stress rating only and functional operation of the device at these or any ...
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AC ELECTRICAL CHARACTERISTICS OVERDRIVE SPEED PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low NOTES: 1. ...