74LVC125APW,112 NXP Semiconductors, 74LVC125APW,112 Datasheet - Page 2

• Manufacturer Part Number: 74LVC125APW,112
• Description: IC BUFF DVR TRI-ST QD 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC125APW,112

• Logic Type: Buffer/Line Driver, Non-Inverting
• Package / Case: 14-TSSOP
• Number Of Elements: 4
• Number Of Bits Per Element: 1
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: 74LVC
• Number Of Channels Per Chip: 4
• Polarity: Non-Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 24 mA
• Input Bias Current (max): 40 uA
• Low Level Output Current: 24 mA
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 8 / 4
• Output Type: 3-State
• Propagation Delay Time: 2.4 ns
• Logical Function: Buffer/Line Driver
• Number Of Elements: 4
• Number Of Channels: 4
• Number Of Inputs: 4
• Number Of Outputs: 4
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Package Type: TSSOP
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.2V
• Quiescent Current: 40uA
• Technology: CMOS
• Pin Count: 14
• Mounting: Surface Mount
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1576-5; 74LVC125APW; 935231720112

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
ORDERING INFORMATION
2003 May 07
t
C
C
74LVC125AD
74LVC125ADB
74LVC125APW
74LVC125ABQ
TYPE NUMBER
PHL
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from 40 to +85 C and 40 to +125 C.
I
PD
Quad buffer/line driver with 5 V tolerant input/outputs;
3-state
P
f
f
C
V
N = total load switching outputs;
SYMBOL
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
2
V
CC
= 25 C; t
f
o
propagation delay nA to nY
input capacitance
power dissipation capacitance per gate V
2
) = sum of the outputs.
I
f
= GND to V
i
TEMPERATURE RANGE
N + (C
r
= t
f
40 to +125 C
40 to +125 C
40 to +125 C
40 to +125 C
PARAMETER
2.5 ns.
L
CC
.
V
CC
2
f
o
) where:
2
C
notes 1 and 2
DESCRIPTION
The 74LVC125A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V.
The 74LVC125A consists of four non-inverting buffers/line
drivers with 3-state outputs (nY) which are controlled by
the output enable input (nOE). A HIGH at nOE causes the
outputs to assume a high-impedance OFF-state.
CC
L
PACKAGES
D
PINS
= 50 pF; V
14
14
14
14
in W).
= 3.3 V;
CONDITIONS
CC
DHVQFN14
PACKAGE
TSSOP14
SSOP14
= 3.3 V 2.4
SO14
4.0
12
TYPICAL
MATERIAL
plastic
plastic
plastic
plastic
Product specification
74LVC125A
ns
pF
pF
SOT108-1
SOT337-1
SOT402-1
SOT762-1
UNIT
CODE