PM4328-PI PMC-Sierra, Inc., PM4328-PI Datasheet - Page 205

• Manufacturer Part Number: PM4328-PI
• Description: Framer, T1|E1|T3 Standard Format, 324-BGA
• Manufacturer: PMC-Sierra, Inc.

STANDARD PRODUCT
DATASHEET
PMC-2011596
PROPRIETARY AND CONFIDENTIAL
ESIG[x]
CECLK
CEFP
ED[x]
In E1 mode EFP[x] may be chosen to indicate alignment of every frame or the
composite CRC and Signaling multiframe alignment as shown in Figure 65, by
setting the EMFP bit in the T1/E1 Serial Interface Configuration register. If parity
checking is enabled, a parity bit should be inserted on ED[x] in the first bit of
each frame.
Figure 66: T1 Egress Interface Clock Slave: External Signaling mode
Figure 67: E1 Egress Interface Clock Slave : External Signaling Mode
The Egress Interface is configured for the Clock slave: External Signaling Mode
by writing to EMODE[2:0] in theT1/E1 Egress Serial Interface Mode Select
register. ED[x] is clocked in on the active edge of CECLK. Frame alignment is
specified by pulses on CEFP. ESIG[x] should carry the signaling bits for each
channel in bits 5,6,7 and 8. These signaling bits will be inserted into the data
stream by the T1 or E1 transmitter. If parity checking is enabled, a parity bit
should be inserted on ED[x] and ESIG[x] in the first bit of each frame. The parity
operates on all bits in the ED[x] and ESIG[x] streams, including the unused bits
on ESIG[x].
ESIG[x]
CECLK
CEFP
ED[x]
1 2 3 4 5 6 7 8 F
Channel 24
1 2 3 4 5 6 7 8
Timeslot 31
A B C D
F-bit or Parity
A B C D
(if enabled)
Parity bit
ISSUE 1
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Channel 1
Timeslot 0
A B C D
1 2 3 4 5 6 7 8
Channel 2
Timeslot 1
192
A B C D
A B C D
1 2 3 4 5 6 7 8 F
Channel 24
1 2 3 4 5 6 7 8
Timeslot 31
A B C D
F-bit or Parity
A B C D
HIGH DENSITY T1/E1 FRAMER
(if enabled)
Parity bit
AND M13 MULTIPLEXER
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Channel 1
PM4328 TECT3
Timeslot 0
A B C D
1